Introduction

There are two CPUs named AP and NP integrated into chip. The inter-processor communication (IPC) hardware is designed to make CPUs communicate with each other. The IPC provides a set of registers for each processor that facilitates inter-processor communication via interrupts. Interrupts may be independently masked by each processor to allow polled-mode operation.

The IPC communication data must be located in a common memory, which is not part of the IPC block.

Features

• Status signaling for the 16 channels (8 channels for Tx and 8 channels for Rx)

  • Channel empty/full flag, also used as a lock

• Two sets interrupt lines per processor

  • One set for Rx channel full (communication data posted by sending processors)

  • One set for Tx channel empty (communication data retrieved by receiving processors)

• Interrupt masking per channel

  • Channel Tx empty mask

  • Channel Rx full mask

• Four hardware semaphores for atomic operation of shared resources

Architecture

The IPC provides a means for simple communication among CPUs. It can use shared SRAM to transmit information to each other. The system block diagram of IPC is depicted below.

The IPC submodule’s structure of each processor is the same. The following figure summarizes the submodule’s structure of IPC_NP. Each processor has two sets of transmission channels, one for transmitting data (Tx) to another CPU, and one for receiving data (Rx) from another CPU. An Interrupt Status Register (ISR) is used to present current channel Tx empty or Rx full status change, an Interrupt Mask Register (IMR) is used to enable interrupts for Tx empty or Rx full, and an Interrupt Clear Register (ICR) is used to clear the corresponding interrupts. The submodule’s structure of IPC_AP is similar.

Functional Description

Message Transmit

As there are two CPUs in this chip, each CPU has a set of Tx channels to send data to another CPU, and a set of Rx channels to receive requests from another CPU. Each set contains 16 channels. Channel index of Tx channels and the corresponding Rx channels are one-to-one mapping.

IPC message transmission mapping (Tx) shows the IPC transmission mapping from NP to AP, and IPC message receive mapping (Rx) shows the IPC receive mapping of NP from AP.

• REG_TX_DATA_N2A is used for NP to transmit data to AP, once bit 1 is written to the channel x (x = 0, 1, …, 15), the corresponding bit in target REG_RX_DATA_N2Ax will be set. The Rx full bit of channel x in REG_ISR_AP will be set at the same time.

• Writing bit 1 to channel x in REG_ISR_AP clears the Rx full interrupt of channel x, the corresponding channel x Tx empty interrupt bit in REG_ISR_NP will be set automatically.

IPC message transmission mapping (Tx)

IPC message receive mapping (Rx)

Interrupts

Interrupt for Normal Usage

There are totally 32 receive and transmit interrupts with maskable interrupts for each processor. IPC NVIC of AP will be connected to NP for a quick power-resume issue.

If you want to transmit a message from CPUn to CPUm (\(n ≠ m\)), after preparing data in a common memory, write bit 1 to the channel x of REG_TX_DATA_n2m.

1. The data will be mapped to the REG_RX_DATA_n2mx of CPUm.

2. If REG_ISR_TX_EMPTY_INTR_STATUS_n2mx in REG_ISR_n is set, it will be cleaned automatically.

3. The REG_ISR_RX_FULL_INTR_STATUS_n2mx in REG_ISR_m will be set automatically.

4. If the REG_ISR_RX_FULL_INTR_MASK_n2mx is enabled in REG_IMR_m and IPC interrupt is enabled in NVIC, thus announce the IPC_IRQ interrupt to the CPUm.

After handling the message from CPUn, CPUm can write ‘1’ to REG_ISR_RX_FULL_INTR_STATUS_n2mx in REG_ISR_m.

1. The REG_ISR_RX_FULL_INTR_STATUS_n2mx in REG_ISR_m will be cleaned.

2. The REG_ISR_TX_EMPTY_INTR_STATUS_n2mx in REG_ISR_n will be set automatically.

3. If the REG_ISR_TX_EMPTY_INTR_MASK_n2mx is enabled in REG_IMR_n and IPC interrupt is enabled in NVIC, thus announce the IPC_IRQ interrupt to the CPUn.

4. The channel x bit in REG_RX_DATA_n2m and REG_TX_DATA_n2m will be cleaned automatically.

Interrupt for Wakeup

In chip, the power of AP is controlled by NP, and NP can be KM4 or KR4 according to user’s configuration. Only NP knows the status of AP. If an wakeup interrupt is triggered in AP and AP is in sleep mode at this time, it is necessary to notify NP to power on AP. The fastest way is to connect the interrupt of IPC_AP and other AP wakeup INT to the AP wake mask of NP and enable it. When IPC_AP receives the data to trigger the interrupt, NP will immediately enter the IRQ of AP_WAKE to power on AP, and then AP can process the received message. The same for KM4. The following figure illustrates the IPC interrupt requests.

The IPC interrupt software handler flow is shown below.

General Usage

IPC without Handshake

As there are Rx full and Tx empty interrupts for each processor, these functions can be used to realize message transmission and handshake. IPC message transmission flow without handshake shows the interrupt messaging protocol of IPC without waiting for a handshake from receiver. It takes the message transmission from KR4 to KM4 for example.

The following table shows IPC message transmission steps without handshake

IPC message transmission steps without handshake

Step	Description
1	Check the Tx data status of the channel 0 in KR4 IPC Tx Data Register
2	KR4 writes data to the Common Memory
3	Write 1 to idle channel 0 in IPC Tx Data Register
4	The KR4 IPC Tx Data Register write operation Map to KM4 IPC Rx Data Register Clear the Tx empty interrupt bit in the KR4 Interrupt Status Register Set the Rx full bit in the KM4 Interrupt Status Register
5	If the Rx full interrupt mask is enabled in KM4 Interrupt Mask Register, a Rx full interrupt request will be generated to KM4.
6	After checking Rx full channel, KM4 performs a data read from the corresponding Common Memory
7	After finishing the interrupt handler, KM4 writes 1 to KM4 Interrupt Status Register to clear the Rx full interrupt
8	The KM4 Interrupt Status Register write operation Clear the Rx full interrupt status bit in the KM4 Status Register Set Tx empty interrupt status bit in the KR4 Status Register
9	Clear the channel 0 bit in KM4 IPC Rx Data Register and KR4 IPC Tx Data Register automatically

IPC message transmission flow without handshake

IPC with Handshake

IPC message transmission flow with handshake shows the interrupt messaging protocol of IPC with waiting for a handshake from receiver. It takes the message transmission from KR4 to KM4 for example.

The following table shows IPC message transmission steps with handshake

IPC message transmission steps with handshake

Step	Description
1	Check the Tx data status of the channel 0 in KR4 IPC Tx Data Register
2	KR4 writes data to the Common Memory
3	Write 1 to idle channel 0 in IPC Tx Data Register.
4	The KR4 IPC Tx Data Register write operation Map to KM4 IPC Rx Data Register Set the Rx full bit in the KM4 Interrupt Status Register
5	If the Rx full interrupt mask is enabled in KM4 Interrupt Mask Register, a Rx full interrupt request will be generated to KM4.
6	After checking Rx full channel, KM4 performs a data read from the corresponding Common Memory
7	After finishing the interrupt handler, KM4 write 1 to KM4 Interrupt Status Register to clear the Rx full interrupt
8	The IPC Interrupt Status Register write operation Clear the Rx full interrupt status bit in the KM4 Status Register Set Tx empty interrupt status bit in the KR4 Status Register
9	Clear the channel 0 bit in KM4 IPC Rx Data Register and KR4 IPC Tx Data Register automatically
10	If Tx empty mask is enabled in KR4 Interrupt Mask Register, the setting of the Tx empty bit in the KR4 Status Register generates a Tx Empty interrupt to KR4
11	KR4 writes 1 to KR4 Interrupt Status Register to clear the Tx full interrupt

IPC message transmission flow with handshake

Registers

The following table lists the memory map of the IPC and sema registers. The base addresses are: IPC0: 0x4081_5000 IPC1: 0x4081_5080 Sema: 0x4081_5200

Name	Address offset	Access	Description
REG_IPC_DATA	000h	R/W	Take LP’s IPC as an example to describe the function of IPC’s internal registers.The REG_TX_DATA is used to transmit message from LP to NP or AP. (The logic cannot be generated automatically)
REG_IPC_ISR	004h	R/W	This register is used to record Tx empty
REG_IPC_IMR	008h	R/W
REG_IPC_ICR	00Ch	R/W	This register can ensure that the software can manually clear the Tx register in an emergency.
REG_IPC_SEM_0	020h	R
REG_IPC_SEM_1	024h	R
REG_IPC_SEM_CPUID0	028h	R
REG_IPC_SEM_CPUID1	02Ch	R
REG_IPC_SEM_CPUID2	030h	R
REG_IPC_SEM_CPUID3	034h	R
REG_IPC_DUMMY	038h	R/W

REG_IPC_DATA

• Name : Tx_Rx Register

• Size : 32

• Address offset : 000h

• Read/write access : R/W

Take LP’s IPC as an example to describe the function of IPC’s internal registers.The REG_TX_DATA is

used to transmit message from LP to NP or AP.

(The logic cannot be generated automatically)

Bit	Symbol	Access	Reset	Description
31:16	TX0_DATA	R/W	0x0	After preparing descriptor, data and corresponding memory, 1: Writing 1 to the Tx data register (tx0_data) channel x bit, and the data will be mapped to the CPU0’s RX data reg ister (rx0_data) channel x bit. And the corresponding Rx full status bit in REG_ISR_CPU0 will be set. 0: Writing 0 has no effect. If the corresponding Rx full status bit in REG_ISR_CPU0 (eg. isr_rx0_full_status6) is cleared, the corresponding bit in t x0_data will be cleaned automatically.
15:0	RX0_DATA	R	0x0	Rx data automatically maps data from tx0_data of CPU0

REG_IPC_ISR

• Name : Interrupt Empty Full Status Register

• Size : 32

• Address offset : 004h

• Read/write access : R/W

This register is used to record Tx empty

Bit	Symbol	Access	Reset	Description
31	ISR_TX0_EMPTY_STATUS15	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
30	ISR_TX0_EMPTY_STATUS14	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
29	ISR_TX0_EMPTY_STATUS13	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
28	ISR_TX0_EMPTY_STATUS12	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
27	ISR_TX0_EMPTY_STATUS11	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
26	ISR_TX0_EMPTY_STATUS10	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
25	ISR_TX0_EMPTY_STATUS9	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
24	ISR_TX0_EMPTY_STATUS8	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
23	ISR_TX0_EMPTY_STATUS7	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
22	ISR_TX0_EMPTY_STATUS6	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
21	ISR_TX0_EMPTY_STATUS5	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
20	ISR_TX0_EMPTY_STATUS4	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
19	ISR_TX0_EMPTY_STATUS3	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
18	ISR_TX0_EMPTY_STATUS2	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
17	ISR_TX0_EMPTY_STATUS1	R/W	0x0	Refer to the description of the isr_tx0_empty_status0
16	ISR_TX0_EMPTY_STATUS0	R/W	0x0	Tx channel 0 empty interrupt status of CPU1 transmit to CPU 0. If the corresponding Rx full status bit in REG_ISR_CPU0 ( eg.isr_rx0_full_status0) is cleared, the corresponding Tx em pty status bit will be set automatically. It will be cleared by software writing 1.
15	ISR_RX0_FULL_STATUS15	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
14	ISR_RX0_FULL_STATUS14	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
13	ISR_RX0_FULL_STATUS13	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
12	ISR_RX0_FULL_STATUS12	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
11	ISR_RX0_FULL_STATUS11	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
10	ISR_RX0_FULL_STATUS10	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
9	ISR_RX0_FULL_STATUS9	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
8	ISR_RX0_FULL_STATUS8	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
7	ISR_RX0_FULL_STATUS7	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
6	ISR_RX0_FULL_STATUS6	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
5	ISR_RX0_FULL_STATUS5	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
4	ISR_RX0_FULL_STATUS4	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
3	ISR_RX0_FULL_STATUS3	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
2	ISR_RX0_FULL_STATUS2	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
1	ISR_RX0_FULL_STATUS1	R/W	0x0	Refer to the description of the isr_rx0_full_status0.
0	ISR_RX0_FULL_STATUS0	R/W	0x0	Rx channel 0 full interrupt status of CPU1. The correspondin g Rx full status bit will be set by CPU0’s Tx data register (tx0_data) channel 0. It will be cleared by software writing 1.

REG_IPC_IMR

• Name : Interrupt Empty Full Mask Register

• Size : 32

• Address offset : 008h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:16	IMR_TX0_EMPTY_MASK	R/W	0x0	0: Mask Tx Channel x empty interrupt of CPU1 transmit to CPU0 1: Unmask Tx Channel x empty interrupt of CPU1 transmit t o CPU0
15:0	IMR_RX0_FULL_MASK	R/W	0x0	0: Mask Rx Channel x full interrupt of CPU1 received from CPU0 1: Unmask Rx Channel x full interrupt of CPU1 received fr om CPU0

REG_IPC_ICR

• Name : Clear Tx Register

• Size : 32

• Address offset : 00Ch

• Read/write access : R/W

This register can ensure that the software can manually clear the Tx register in an emergency.

Bit	Symbol	Access	Reset	Description
31	ICR_TX0_DATA_CLEAR15	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
30	ICR_TX0_DATA_CLEAR14	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
29	ICR_TX0_DATA_CLEAR13	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
28	ICR_TX0_DATA_CLEAR12	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
27	ICR_TX0_DATA_CLEAR11	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
26	ICR_TX0_DATA_CLEAR10	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
25	ICR_TX0_DATA_CLEAR9	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
24	ICR_TX0_DATA_CLEAR8	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
23	ICR_TX0_DATA_CLEAR7	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
22	ICR_TX0_DATA_CLEAR6	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
21	ICR_TX0_DATA_CLEAR5	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
20	ICR_TX0_DATA_CLEAR4	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
19	ICR_TX0_DATA_CLEAR3	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
18	ICR_TX0_DATA_CLEAR2	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
17	ICR_TX0_DATA_CLEAR1	R/W	0x0	Refer to the description of the icr_tx0_data_clear0.
16	ICR_TX0_DATA_CLEAR0	R/W	0x0	0: Writing 0 has no effect. 1: Clear the Tx data register (tx0_data) channel 0 bit.
15:0	RSVD0	R/W	0x0

REG_IPC_SEM_0

• Size : 32

• Address offset : 020h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	SEM_0_DATA	R	0x0	It is used to indicate who owns this semaphore .

REG_IPC_SEM_1

• Size : 32

• Address offset : 024h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	SEM_1_DATA	R	0x0	It is used to indicate who owns this semaphore .

REG_IPC_SEM_CPUID0

• Size : 32

• Address offset : 028h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	SEM_CPUID0_DATA	R	0x0	It is used to indicate cpuid of this semaphore .

REG_IPC_SEM_CPUID1

• Size : 32

• Address offset : 02Ch

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	SEM_CPUID1_DATA	R	0x0	It is used to indicate cpuid of this semaphore .

REG_IPC_SEM_CPUID2

• Size : 32

• Address offset : 030h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	SEM_CPUID2_DATA	R	0x0	It is used to indicate cpuid of this semaphore .

REG_IPC_SEM_CPUID3

• Size : 32

• Address offset : 034h

• Read/write access : R

Bit	Symbol	Access	Reset	Description
31:0	SEM_CPUID3_DATA	R	0x0	It is used to indicate cpuid of this semaphore .

REG_IPC_DUMMY

• Size : 32

• Address offset : 038h

• Read/write access : R/W

Bit	Symbol	Access	Reset	Description
31:16	RSVD	R	-	Reserved
15:0	DUMMY	R/W	0x0	Dummy reg