Introduction

The CHIP_EN (chip enable) is an external pin that can be used to control the reset status of the whole SoC. This pin can work in level reset mode, interrupt reset mode or pulse reset mode. By default, it works in level reset mode. This pin always has the function of resetting system no matter in which mode.

• Level reset mode: reset the chip once detects low on CHIP_EN pin, and exit reset after CHIP_EN goes high.

• Interrupt reset mode: fire an interrupt when low detect, and trigger reset if the interrupt isn’t cleared with the response time.

• Pulse reset mode: reset the chip once detecting low on CHIP_EN pin, and exit reset immediately.

When the system works in interrupt reset mode, software needs to clear the interrupt within the pre-defined time once the CHIP_EN is pressed. If the software crashes and cannot clear the interrupt in the pre-defined time, hardware will reset the system.

The software interrupt mode is mainly used in the power save scenario. This is illustrated in the following figure. The CHIP_EN pin just likes the power button of the smartphone: a short press will trigger the system to enter low power mode or wake up the system; a long press will trigger the system reboot.

One user scenario for pulse reset mode is to reset the device to factory settings. This is illustrated in the following figure. The CHIP_EN pin of the SoC just likes the reset button in the router. From the user’s view, a short press will trigger the device reboot, and a long press will reset the device to factory settings. Actually, resetting the device to factory settings is a software behavior; the device will reboot once the CHIP_EN is pressed, and in its initial power flow, it will check the CHIP_EN status. If this pin keeps in low for more than pre-defined time, software will reset the device to factory settings.

By default, the CHIP_EN pin works in level reset mode, software can configure it to software mode in the bootloader or the application. Before configuration, the CHIP_EN can only work in level reset mode.

备注

• The CHIP_EN can reset the whole system in any conditions without the help of software.

• The CHIP_EN can control the SWR or other power sources in the right order, even the out-chip circuit uses the internal power source. The CHIP_EN reset has the ability to reset the external chips and to guarantee them work properly.

Debounce Function

Debounce function can be enabled by configuring debounce settings; this function is enabled by default with a setting of 100us for TDB, the debounce time can be configured from 100us to 16ms. Only when a continual low or high lasts longer than TDB will the hardware recognize it as a low or high. hardware will ignore the glitch that is shorter than TDB.

Debounce function can work well in level reset mode, interrupt reset mode and pulse reset mode, the function of debounce is shown in the following figure.

Level Reset Mode

The hardware works in level reset mode by default. When initial power-on, once the chip enable pad rises to high value, the system reset will be released and hardware PMC will power on the system.

The timing sequence of the initial power-on is illustrated in the following figure.

The CHIP_EN will continue to work in reset mode if no software configuration. In level reset mode, the whole system will be reset once a low level is detected on CHIP_EN. Moreover, it keeps in power-down mode until a high level is detected.

Interrupt Reset Mode

The CHIP_EN can be configured to work in interrupt reset mode. In interrupt reset mode, a level change in CHIP_EN will trigger an interrupt instead of resetting the system.

If the time of CHIP_EN keeps low longer than a short press threshold, a short press interrupt will be triggered. If it keeps low longer than a long press threshold, a long press interrupt will be triggered.

The long-press event should be acknowledged within Tack; otherwise, the system will reset. Behaviors will be illustrated in the following sections; the signal of CHIP_EN means the signal after debounce.

Case 1: button press time shorter than Tsp

In this case, no interrupt is triggered, just like nothing happens, as shown in the following figure.

Case 2: short press time longer than Tsp and shorter than (Tsp+Tlp)

In this case, an interrupt will be triggered with short-press event, as shown in the following figure. If the short press interrupt happens in the sleep mode, this interrupt will also wake up the system with a wake-up reason indicating the wake-up event.

Case 3: long press and system acknowledge to the interrupt

In this case, the press time is longer than (Tsp+Tlp), an interrupt will be triggered with a short-press event first, and then a long-press event, as shown in the following figure.

If software works properly, it can clear the long press event; otherwise, the hardware will reset the whole system if no acknowledgment after Tack. After software clears the interrupt, no matter how long the button is pressed, there will not be other interrupts.

If the long press interrupt happens in the sleep mode, this interrupt will also wake up system with a wake-up reason indicating the wake-up event.

Case 4: long press and no acknowledge

In this case, the system will reset the system after (Tsp + Tlp + Tack) if the CHIP_EN stays low and software does not clear the interrupt, and keeps in reset mode until CHIP_EN goes to high, as shown in the following figure.

When the system boots up after CHIP_EN reset, the settings of CHIP_EN are also reset The CHIP_EN will work in level reset mode until software configures it again.

备注

If CHIP_EN stays low when a reset is triggered in software reset mode, the chip will stay in reset mode until CHIP_EN goes high from low.

Only when the CHIP_EN stays low longer than (Tsp + Tlp + Tack) can CHIP_EN reset the system. Otherwise, the system cannot be reset. The case shown in the following figure cannot trigger system reset.

Pulse Reset Mode

In order to realize the function of long press to restore factory settings and short press to reset the system directly, the pulse reset mode is added.

The difference between pulse reset mode and level reset mode is that in pulse reset mode the system reboot immediately (in level reset mode, the system reboots after CHIP_EN goes to high). This feature gives software the ability to count the key press period to distinguish short and long press.

Registers

The base address of CHIP_EN registers is 0x4080_A000.

Name	Offset	Access	Description
REG_AON_CHIPEN_CTRL	0x50	R/W	CHIP_EN Function Control Register
REG_AON_CHIPEN_ISR	0x54	R/W1C	CHIP_EN Interrupt Clear Register

REG_AON_CHIPEN_CTRL

• Name: CHIP_EN Function Control Register

• Size: 32 bits

• Address offset: 0x50

• Read/write access: read/write

Bit	Symbol	Access	Reset	Description
31:19	RSVD	-	-	Reserved
18	CHIPEN_ST	R	0	CHIP_EN pin status 0: Logic ‘0’ on the CHIP_EN pin 1: Logic ‘1’ on the CHIP_EN pin
17:16	CHIPEN_INTR_MODE	R/W/ES	0	Chipen operation mode 00: Reset mode. When chipen pad low, hw will reset all chip. 01: Interrupt mode. It will enable short/long press function. 1x: Pulse reset mode. The transation from other value to 2’d2 will gen a posedge to set RST_PILSE_EN in HV domain. Once in pulse reset mode, this field can’t be modified again, and always read out 2’b11.
15:14	RSVD	-	0	Reserved
13:12	CHIPEN_TACK	R/W	0	00: 50ms 01: 100ms 10: 200ms 11: 400ms
11	RSVD	-	-	Reserved
10:8	CHIPEN_TLP	R/W	0	000: 1000ms 001: 1500ms 010: 2000ms 011: 2500ms 100: 3000ms 101: 3500ms 110: 4000ms 111: 4500ms
7	RSVD	-	-	Reserved
6:4	CHIPEN_TSP	R/W	0	000: 0ms 001: 50ms 010: 100ms 011: 150ms 100: 200ms 101: 250ms 110: 300ms 111: 350ms
3	RSVD	-	-	Reserved
2:0	CHIPEN_TDBC	R/W	001	000: 0us 001: 100us 010: 500us 011: 1000us 100: 2000us 101: 4000us 110: 8000us 111: 16000us

REG_AON_CHIPEN_ISR

• Name: CHIP_EN Interrupt Clear Register

• Size: 32 bits

• Address offset: 0x54

• Read/write access: Read/write to clear

Bit	Symbol	Access	Description
31:2	RSVD	-	Reserved
1	CHIPEN_LP_ISR	R/W1C	Chipen long press interrupt status. 0:no interrupt 1:interrupt occurs. Write ‘1’ to clear the flag.
0	CHIPEN_SP_ISR	R/W1C	Chipen long press interrupt status. 0:no interrupt 1:interrupt occurs. Write ‘1’ to clear the flag.