Nested Vector Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is closely integrated with the core to achieve low-latency interrupt processing. All the interrupts including the core exceptions are managed by the NVIC.

The NVIC contains the following features:

  • The NVIC is an integral part of each CPU.

  • Tightly-coupled interrupt controller provides low interrupt latency.

  • The NVIC controls system exceptions and peripheral interrupts.

  • The NVIC of the KM4TZ supports:

    • 79 vectored interrupts

    • 8 programmable interrupt priority levels with hardware priority level masking

    • Vector table offset register (VTOR)

    • Secure NVIC and non-secure NVIC

  • The NVIC of the KM4NS supports:

    • 72 vectored interrupts

    • 4 programmable interrupt priority levels with hardware priority level masking

    • Vector table offset register (VTOR)

  • Support for NMI from any interrupts

The NVIC and the processor core are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

For more information about exceptions and NVIC programming, refer to Arm® Cortex®-M33 Processor Technical Reference Manual.

Interrupt List

The following table lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. The interrupt number does not imply any interrupt priority.

Function

KM4NS INT#

KM4TZ INT#

WAKE_MASK

WIFI_FISR_FESR_IRQ

0

0

0

WIFI_FTSR_MAILBOX_IRQ

1

1

1

WL_DMA

2

2

WL_PROTOCOL

3

3

AP_WAKE_IRQ

4

4

2

IPC_KM4NS

5

3

IPC_KM4TZ

5

4

IPC_BT_CPU

IWDG

6

6

5

Timer0

7

7

6

Timer1

8

8

7

Timer2

9

9

8

Timer3

10

10

9

Timer4

11

11

Timer5

12

12

Timer6

13

13

Timer7

14

14

Timer8

15

15

COEX_MAILBOX

16

16

RSVD

17

17

PMC_Timer0

18

18

10

PMC_Timer1

19

19

11

UART0

20

20

12

UART1

21

21

13

UART2

22

22

14

UART3

23

23

15

UART_LOG

24

UART_LOG

24

UART_LOG

16

GPIOA

25

25

17

GPIOB

26

26

18

GPIOC

27

27

19

I2C0

28

28

I2C1

29

29

GDMA0_Channel0

30

30

GDMA0_Channel1

31

31

GDMA0_Channel2

32

32

GDMA0_Channel3

33

33

GDMA0_Channel4

34

34

GDMA0_Channel5

35

35

GDMA0_Channel6

36

36

GDMA0_Channel7

37

37

SPI0

38

38

SPI1

39

39

SPORT0

40

40

RTC

41

41

22

ADC

42

42

23

ADC_COMP

43

43

CAP_TOUCH

44

44

25

THERMAL

45

45

BOR

46

46

26

PWR_DOWN

47

47

27

RMII

48

48

LCDC

49

49

MJPEG

50

50

PPE

51

51

PKE

52

52

TRNG

53

53

AON_TIMER

54

54

29

AON_WAKEPIN

55

55

30

SDIO_WIFI

56

56

31

SDIO_BT

57

57

32

SDIO_HOST

58

58

33

USB

59

59

34

CAN0

60

60

35

CAN1

61

61

36

IR

62

62

RXI300

63

63

PSRAMC

64

64

SPI_FLASH

65

65

RSIP

66

66

AES

67

67

SHA

68

68

AES_S

SHA_S

KM4NS_WDG

69

KM4TZ_NS_WDG

69

KM4TZ_S_WDG

70

OCP

71

SPIC_ECC

72

UVC_DEC

73

RTC_DET

74

BT_MAILBOX

70

75

BT_SCB

71

76

37

BT_WAKE_HOST

72

77

38

KM4NS_WDG_RST

78