IC: RTL8721Dx RTL8720E RTL8726E RTL8713E RTL8730E RTL8721F

Overview

To enhance design flexibility with limited pin resources, this chip provides Pin Multiplexing (Pinmux) functionality. Each pin can be configured to connect to different internal IP circuits.

For specific pin-to-IP circuit mapping relationships, please refer to the URL shown in the Function Multiplexing Pinmux Table below.

The Pinmux Table provides the following key information:

• Pin distribution under different part numbers

• On-chip peripheral signals connectable to each pin

• Allocation of power-on latch pins (Trap Pins)

• Default pin assignments for J-Link debug interface (SWD)

• Default pin assignments for firmware download, command interaction, and logging function (LOGUART)

• Power supply information for each I/O pin

Function Multiplexing

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Usage Method

Developers can connect pins to specified on-chip peripheral signals by calling the programming interface Pinmux_Config(PinName, PinFuncID).

Parameter description:

PinName:

Pin identifier

PinFuncID:

Specified signal ID of the on-chip peripheral controller

Based on the configured function-id, pins can either output internal chip signals to external devices or receive signals input from external devices to internal chip modules.

For specific pin to function-id mappings, please refer to {{IC_PARAM_PINMUX_DOWNLOAD_URL_EN}}.

Function ID

• Function ID 0~{{IC_PARAM_FUNCID_DEDICATE_END}}

  When Function ID is 0~{{IC_PARAM_FUNCID_DEDICATE_END}}, each pin can only connect to fixed signals of specific IPs. These pins have limited configurable functions, but dedicated designs can maximize the performance of each IP module.

  Note

  For example, both Function ID {{IC_PARAM_FUNCID_DEDICATE_END}} and Function IDs {{IC_PARAM_FUNCID_FULL_MATRIX_SPI1_CLK}}~{{IC_PARAM_FUNCID_FULL_MATRIX_SPI1_CS}} represent SPI functions.

  • Function ID {{IC_PARAM_FUNCID_DEDICATE_END}} uses dedicated pins, enabling SPI function to achieve maximum rate of 50MHz (master mode).

  • Function ID {{IC_PARAM_FUNCID_FULL_MATRIX_SPI1_CLK}}~{{IC_PARAM_FUNCID_FULL_MATRIX_SPI1_CS}} (full-cross pins) can only achieve maximum rate of 12.5MHz (master mode).

  Take PB30 as an example: When configured with Function ID 1, this pin will be directly connected to the UART1_RXD signal of UART1 through pin multiplexing.

  Refer to the {{IC_PARAM_PINMUX_DOWNLOAD_URL_EN}} for specific function assignments supported by each pin.

  

  PB30 pin multiplexing connection diagram

• Function ID {{IC_PARAM_FUNCID_FULL_MATRIX_START}}~{{IC_PARAM_FUNCID_FULL_MATRIX_END}}

  When Function ID is {{IC_PARAM_FUNCID_FULL_MATRIX_START}}~{{IC_PARAM_FUNCID_FULL_MATRIX_END}}, each pin can connect to different signals of specific IPs. This design provides greater configuration flexibility, but with limitations in application scope and performance (e.g., maximum transmission rate) of some IP modules.

  Take PA27 as an example:

  • When configuring Function ID of PA27 as 19, it connects to UART0_TXD signal of UART0;

  • When configuring Function ID of PA27 as 20, it connects to UART0_RXD signal of UART0.

  Refer to the {{IC_PARAM_PINMUX_DOWNLOAD_URL_EN}} for specific configurations.

  

  PA27 pin multiplexing connection diagram

Trap Pins

Caution

Before development, pay special attention to the following pin multiplexing considerations to avoid unexpected behavior.

During chip power-on, internal circuits latch the states of specific pins to determine operational modes.

The following table lists all trap pins and their descriptions:

RTL8721DxRTL8720ERTL8726ERTL8713ERTL8730ERTL8721F

Pin name	Symbol	Active level	Description
PB31	TM_DIS	Low	Disables test mode, with default internal pull-up. This pin is for internal testing only. Maintain logic high during normal operation. 1: Normal operation mode 0: Test mode
PB5	UD_DIS	Low	Disables UART download mode, with internal pull-up by default. Download mode disable is controlled by OTP-related fields. When OTP disables UART download mode, the pin’s power-on latch state becomes invalid. 1: Enter normal boot mode 0: Enter UART download mode

Note

Trap pins require external pull-up/pull-down voltages according to I/O power supply selection.

Wake Pins

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• General GPIO pins support waking the system from CG and PG sleep modes.

• Wake-up pins (PB30 and PB31) are directly connected to wake-up circuits, and can wake the system from DSLP mode in addition to CG and PG modes.

Warning

• Disable wake-up functionality before multiplexing these two pins.

• Wake-up pins may be multiplexed with Trap pins.

  When multiplexing, ensure the Trap pin’s signal level after wake-up does not cause the system to enter unexpected modes.

SWD Pins

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Pins {{IC_PARAM_SWD_CLK_PIN}} and {{IC_PARAM_SWD_DATA_PIN}} are forcibly locked to the SWD function by default.

If you want to multiplex these two pins, you must first disable the SWD function, which is already handled by the programming interface Pinmux_Config().

Note

When the following log message appears, it indicates that {{IC_PARAM_SWD_CLK_PIN}} or {{IC_PARAM_SWD_DATA_PIN}} has been connected to another module, and you can no longer connect the debugger via that pin.

If you still need to connect the debugger, please refer to Function Multiplexing to reconfigure the pins for the SWD signals.

SWD PAD PortX_PinYY is configured to funcIDZZ