Supported ICs

Ameba SoC	RTL8721Dx	RTL8720E	RTL8726E	RTL8713E	RTL8730E	RTL8721F
Supported	Y	N	N	N	Y	Y

Introduction

The Infrared Radiation (IR) module is a controller for infrared transmission and reception.

This module provides:

• Hardware modulation for infrared transmission

• Hardware auto-capture for reception

• Supporting half-duplex communication

Working Principle

To streamline the infrared signal model, infrared signals are categorized into two main symbol types:

Carrier Symbol:

• Signal with multiple cycles of the carrier frequency in a set time period

• Represents the modulated signals that physically propagate through the medium

Space Symbol

• Signal that maintains either a continuous high or low level for a defined duration

• Embodies the digital signal either prior to modulation or following demodulation.

IR signal model

Operating Modes

IR module supports both transmission and reception modes.

The operating modes of the infrared module are shown in the table below：

Operating Mode	Core Function	Technical Features	Signal Chain Features
Transmission Mode	Infrared signal generation and modulation	Supports programmable control of carrier parameters	Digital signal → Carrier modulation → Infrared transmission
Reception Mode	Infrared signal capturing and demodulation	Compatible with two types of receiver front-end architectures	Infrared signal → Baseband recovery → Digital decoding

Transmission Mode

This section introduce how to set up the IR Module in Transmission (TX) Mode

• Configure Carrier Frequency:

  • Action: Set a specific carrier frequency using software parameters

  • Purpose: Ensure that the infrared signals are modulated at the correct frequency for successful transmission

• Write Data to TX FIFO:

  • Action: Write data into the TX FIFO through software

  • Purpose: Control the duration of high/low level signals in spatial symbols

TX workflow diagram

How to Parse Data in the TX FIFO

The TX FIFO data is 32-bit wide and contains the following information:

Bit Field Descriptions

Bit Field	Description
BIT[31]	Send carrier or not 1: Send 0: Not-send
BIT[30]	End-Of-Transmission Flag 1: Indicates the last packet in a series of transmissions 0: Indicates a normal packet
BIT[29:28]	Compensation Mode 0: Use system clock to calculate no-carrier cycle number 3: Use compensation clock to calculate no-carrier cycle number 1, 2: Not recommended
BIT[27:0]	Carrier Cycle Count Specifies the number of carrier/no-carrier cycles for the signal duration

BIT[27:0] = fcarrier * Tduration

Parameters：

fcarrier:

Represents the carrier frequency(Unit：Hz)

Tduration:

Represents the duration of carrier or no carrier symbol (Unit：Second)

Next, using the NEC coding protocol, with a carrier frequency of 38kHz and compensation mode0 as an example, to illustrate how to organize data written into the TX FIFO.

Introduction to NEC Encoding Protocol

The NEC encoding protocol symbol sequence:

• 2 Leading Symbols: Used to initiate communication

• 64 Data Symbols: Represent the actual data being transmitted

• 1 Stop Symbol: Indicates the end of transmission

Logic 1:

560μs high, then (2250-560)μs low

Logic 0:

560μs high, then (1120-560)μs low

NEC modulation

How to Organize Data Written to the TX FIFO

• To transmit a logic 1, write the following two entries to the TX FIFO:

  :width: 100% :widths: auto

  Entry	BIT[31]	BIT[30]	BIT[29:28]	BIT[27:0]
  First	1	0	0	38 * 560 / 1000 = 21
  Second	0	0	0	38 * (1690 - 560) / 1000 = 63

• To transmit a logic 0, write the following two entries to the TX FIFO:

  :width: 100% :widths: auto

  Entry	BIT[31]	BIT[30]	BIT[29:28]	BIT[27:0]
  First	1	0	0	38 * 560 / 1000 = 21
  Second	0	0	0	38 * (1120 - 560) / 1000 = 21

• To transmit the stop symbol:

  The stop symbol should be written as the last packet to the TX FIFO; therefore, BIT[30] should be set to 1 to indicate the end of transmission.

  :width: 100% :widths: auto

  Entry	BIT[31]	BIT[30]	BIT[29:28]	BIT[27:0]
  First	1	1	0	38 * 560 / 1000 = 21

Reception Mode

The IR receiver module supports two distinct operational modes, each utilizing specific hardware frontend.

• Learning Mode:

  • Features infrared diodes

  • The RX input signal retains the carrier wave, allowing the IR core to capture carrier symbols

  • Software is responsible for demodulating and decoding the signal to extract key information, such as carrier frequency and duty cycle.

• Normal Reception Mode:

  • Uses infrared receiver modules

  • The frontend removes the carrier wave, enabling the IR core to receive space symbols directly

  • Eliminates the need for software demodulation, thereby simplifying subsequent data processing

RX process flow diagram: comparison of IR Receiver Module vs. IR Diode Frontend

How to Parse Data in RX FIFO

The RX FIFO stores data in a 32-bit wide format, consisting of two information fields:

• BIT[31]: Indicates the received signal level

  • 1: a high level signal

  • 0: a low level signal

• BIT[30:0]: Represents the duration (in sampling clock cycles) of the signal at the current level

Example of RX FIFO data at 10MHz sampling rate (sampling clock period: 100ns) is listed below:

Data	Value	Description
Data 1	0x1001000	high-level signal of approximately 409.6 μs
Data 2	0x00a1644	low-level signal of approximately 66.106 ms

Conditions for Starting Reception

IR RX mode supports both manual reception and automatic reception.

• Manual Reception: Allows manual control over the reception process.

• Automatic Reception:

  • Trigger Configuration:

    • Rising edge, falling edge, or any signal change

  • Functionality:

    • The software sets these conditions to initiate automatic reception.

  • Operation:

    • Upon detecting a configured trigger on the RX input signal, the hardware automatically starts the reception process.

• Data Handling:

  • The IR RX module captures:

    • Signal Level: The state of the signal (high or low)

    • Duration: Number of clock cycles the signal maintains a particular state.

  • Storage:

    • Captured data is stored into the RX FIFO for further processing by software.

Conditions for Stopping Reception

The IR RX module will stop reception when the input signal stays at a specified level for a certain duration, as defined by software through interrupt conditions.

Relevant settings include:

a. The signal level condition to stop reception
b. The minimum duration this level must be held
c. Enabling the RX Counter Threshold Interrupt

The interrupt IR_BIT_RX_CNT_THR_INT_STATUS is triggered when:

• The signal level recorded in RX FIFO matches the software-set stop condition

• The duration at that level reaches the preset threshold.

Example

If software is configured to stop on low level and the duration threshold is at least 66.1ms, the interrupt will be triggered when the RX module detects a low level maintained up to the threshold.

      /* Sample Rate: 10MHz  */
IR_InitStruct.IR_Freq = 10000000;

      /* Condition 1: Target signal logic level (e.g. Low) */
IR_InitStruct.IR_RxCntThrType = IR_RX_COUNT_LOW_LEVEL;

      /* Condition 2: The signal remains at this level for at least ~66.1 ms (e.g. 661,000 cycles at 10 MHz) */
IR_InitStruct.IR_RxCntThr = 0xa1644;

      /* Condition 3: Enable RX Counter Threshold Interrupt */
IR_INTConfig(IR_DEV, IR_BIT_RX_CNT_THR_INT_EN, ENABLE);

Example of Mode Configuration

IR Sending

 /* step1: Configure the Pin as TX signal output, e.g., choose PB4 */
 Pinmux_Config(_PB_4, PINMUX_FUNCTION_IR_TX);

 /* step2: Disable the IR module */
 IR_Cmd(IR_DEV, IR_MODE_TX, DISABLE);

 /* step3: Initialize the structure for setting module operating parameters */
 IR_StructInit(&IR_InitStruct);
 IR_InitStruct.IR_Clock = IR_CLOCK_HZ;
 IR_InitStruct.IR_Mode = IR_MODE_TX;
 IR_InitStruct.IR_Freq = 38000;

 /* step4: Write the structure information from step3 into the IR module register */
 IR_Init(IR_DEV, &IR_InitStruct);

 /* step5: Write the data to be sent into the FIFO */
 IR_SendBuf(IR_DEV, pBuf, txlen, FALSE);

 /*step6: Enable IR functionality to start transmitting data*/
 IR_Cmd(IR_DEV, IR_MODE_TX, ENABLE);

 /* step7: Decide whether to write more data into the TX FIFO as needed */
 while (txlen_remaining == 0) {
     /* Process the data to be sent */
     {
           /*
              do something
           */
     }
     IR_SendBuf(IR_DEV, pBuf, txlen, IsLastPacket);
 }

 /* step8: Transmission complete, disable IR */
 IR_Cmd(IR_DEV, IR_MODE_TX, DISABLE);

Note

• Ensure the condition that the TX FIFO data has been completely sent: To determine if all data in the TX FIFO has been sent, poll the register IR_TX_SR for the status bit IR_BIT_TX_FIFO_EMPTY. A value of 1 indicates that the transmission is complete.

• Before enabling IR TX, it is recommended to first write some packets into the TX FIFO, as shown in step 5~6. Meanwhile, software should promptly write data into the TX FIFO to avoid interruptions in the TX FIFO flow.

IR Receiving

/* step1: Configure the Pin as RX signal input, e.g., choose PB4 */
Pinmux_Config(_PB_4, PINMUX_FUNCTION_IR_RX);

/* step2: Disable the IR module */
IR_Cmd(IR_DEV, IR_MODE_RX, DISABLE);

/* step3: Initialize the structure for setting module operating parameters */
IR_StructInit(&IR_InitStruct);
IR_InitStruct.IR_Clock = IR_CLOCK_HZ;
IR_InitStruct.IR_Mode = IR_MODE_RX;
IR_InitStruct.IR_Freq = 10000000; //sample frequency :Hz
IR_InitStruct.IR_RxCntThrType = IR_RX_COUNT_LOW_LEVEL;
IR_InitStruct.IR_RxCntThr = 0xa1644; //66ms

/* step4: Write the structure information from step3 into the IR module register */
IR_Init(IR_DEV, &IR_InitStruct);

/* step5: Register interrupt handler function and enable NVIC interrupt */
InterruptRegister((IRQ_FUN)IR_irq_handler, IR_IRQ, (u32)NULL, IR_IRQ_PRIORITY_TEST);
InterruptEn(IR_IRQ, IR_IRQ_PRIORITY_TEST);

/* step6: Enable module interrupt */
IR_INTConfig(IR_DEV, IR_RX_INT_ALL_EN, ENABLE);

/* step7: Enable IR functionality to start receiving data */
IR_Cmd(IR_DEV, IR_MODE_RX, ENABLE);

/* step8: Respond to interrupt events */
void IR_irq_handler(void)
{
    /* Get interrupt status */
    IntStatus = IR_GetINTStatus(IR_DEV);

    /* Clear interrupt status */
    IR_ClearINTPendingBit(IR_DEV, IntStatus);

    /* If the number of data received in the RX FIFO reaches the preset threshold,
       read the data from the FIFO to memory for subsequent processing */
    if (IntStatus & IR_BIT_RX_FIFO_LEVEL_INT_STATUS) {
        IR_RX_recv();
    }

    /* When reception end signal is identified, disable IR */
    if (IntStatus & IR_BIT_RX_CNT_THR_INT_STATUS) {
        IR_Cmd(IR_DEV, IR_MODE_RX, DISABLE);
    }
}