IC:

Introduction

This chapter mainly introduces various configuration files that require special attention and modification during the development process.

ameba_bootcfg

This section introduces the boot-related configurations including SoC clock switch and boot log.

github source code

ameba_bootcfg.c

The KM4 boots at 200MHz at the BootRom Stage, and switches to a higher frequency during the bootloader Stage.

There are some limitations when changing the SoC clock:

Clock	Frequency	Core voltage
PLL	300MHz ~ 688.128MHz
KM0	≤105MHz	0.9V
KM0	≤115MHz	1.0V
KM4	≤262MHz	0.9V
KM4	≤345MHz	1.0V

Note

By default, the SDK assumes the Flash is powered at 3.3V. And during initialization, it will automatically switch the Flash to the highest speed rate that does not exceed the 104MHz limit.
For wide voltage range ICs, the maximum operating frequency of the Flash should comply with the speed limitations in the 1.65V to 2.3V power supply range. You can refer to ameba_flashcfg to reduce the speed or contact Realtek for assistance.

SoC & PSRAM Clock Set Flow

Check the value of Boot_SocClk_Info_Idx and SocClk_Info[] in ameba_bootcfg.c.

// for km4, max 345MHz under 1.0v, max 262MHz under 0.9v
// for km0, max 115MHz under 1.0v, max 105MHz under 0.9v
// PLL can be 300MHz~688.128MHz
// KM4_CKD range is [1, 8], KM0_CKD range is [1, 16] or USEXTAL
const SocClk_Info_TypeDef SocClk_Info[] = {
   /* PLL_CLK,     Vol_Type,      KM4_CKD,    KM0_CKD,    PSRAMC_CKD*/
   /* This group is to reduce the impact of PSRAM on RF, the frequency is specially selected */
   {PLL_524M,      CORE_VOL_0P9,  CLKDIV(2),  CLKDIV(5),  CLKDIV(2)},  // For SiP Psram
   {PLL_392M,      CORE_VOL_0P9,  CLKDIV(2),  CLKDIV(4),  CLKDIV(1)},  // For SiP Psram
   {PLL_334M,      CORE_VOL_1P0,  CLKDIV(1),  CLKDIV(3),  CLKDIV(1)},  // For SiP Psram
   /* This group is to reduce the impact of Flash on RF, the frequency is specially selected.
      Single die use the same settings. */
   {PLL_512M,      CORE_VOL_0P9,  CLKDIV(2),  CLKDIV(5),  CLKDIV(2)},  // For SiP Flash or single die (No Psram)
   {PLL_400M,      CORE_VOL_0P9,  CLKDIV(2),  CLKDIV(4),  CLKDIV(1)},  // For SiP Flash or single die (No Psram)
   {PLL_334M,      CORE_VOL_1P0,  CLKDIV(1),  CLKDIV(3),  CLKDIV(1)},  // For SiP Flash or single die (No Psram)
   /* The following frequency settings are not adjustable */
   {PLL_480M,      CORE_VOL_0P9,  CLKDIV(2),  CLKDIV(5),  CLKDIV(2)},  // 48M for usb, both For SiP Psram / SiP Flash / single die
   {PLL_677P376M,  CORE_VOL_1P0,  CLKDIV(2),  CLKDIV(6),  CLKDIV(2)},  // Audio
   {PLL_688P128M,  CORE_VOL_1P0,  CLKDIV(2),  CLKDIV(6),  CLKDIV(2)},  // Audio
};

/**
* @brif  SocClk_Info select. One of Valid_Boot_Idx_for_SiP_Psram or Valid_Boot_Idx_for_No_Psram depend on different chip types
* Boot_SocClk_Info_Idx is [0, sizeof(SocClk_Info)), Soc will set socclk by SocClk_Info[Boot_SocClk_Info_Idx]
*/
#ifdef CONFIG_USB_DEVICE_EN
u8 Boot_SocClk_Info_Idx = 6; /* Make sure the PLL_CLK for USB is an integer multiple of 48MHz */
#else
u8 Boot_SocClk_Info_Idx = 6; /* 480M has an acceptable impact on the RF performance of SiP Psram and SiP Flash */
#endif

Due to certain frequencies of PSRAM or Flash interfering with RF, the BOOT_ChipInfo_ClkInfoIdx() function in the bootloaderbootloader_km4.c file only allows indices represented by Boot_SocClk_Info_Idx within the SocClk_Info array.”

Note

It is not recommended to modify SocClk_Info. If frequency combinations outside of SocClk_Info are needed, it is necessary to confirm whether such configurations would affect RF performance.

u32 BOOT_ChipInfo_ClkInfoIdx(void)
{
   /* PSRAM die is wb955 which can run up to 200MHz */
   ...
   return Boot_SocClk_Info_Idx;
}

The Bootloader will configure the SoC voltage and clock according to the definition of SocClk_Info[Boot_SocClk_Info_Idx]. The PSRAMC (twice the PSRAM clock) rate will also be adjusted synchronously with the SoC clock. The clock speeds for other modules will be automatically set to reasonable values by the software based on their maximum operating speeds. The cases where the value of Boot_SocClk_Info_Idx is 0 and 4 serve as examples:

PSRAM type	PSRAM speed	SocClk_Info[x]	Clock Info
No PSRAM		SocClk_Info[4]	PLL: 400MHz KM4: PLL/2 KM0: PLL/4
With PSRAM	≤200MHz	SocClk_Info[0]	PLL: 524MHz KM4: PLL/2 KM0: PLL/5 PSRAMC: PLL/2

Refer to one of the following methods to change the SoC clock if needed.
- Modify Boot_SocClk_Info_Idx to a value within the range of [0, sizeof(SocClk_Info)], then customize the clock configuration information in SocClk_Info [Boot_SocClk_Info_Idx].
Note

Consider the limitations of the hardware and do not set the clock info illogically.
Rebuild the project and download the new image again.

Boot_Agg_En

The Boot_Agg_En is used with Trace Tool to sort out boot logs from different cores. It can be enabled through Boot_Agg_En.

/**
* @brif  Loguart AGG enable or disable
*    FALSE: disable
*    TRUE: enable
*/
u8 Boot_Agg_En = FALSE;

Note

Refer to Chapter Trace Tool for more information.

github source code

ameba_bootcfg.c

The KM4 boots at 150MHz at the BootROM Stage, and switches to a higher frequency during the bootloader Stage.

There are some limitations when changing the SoC clock:

Clock	Frequency	Core voltage
PLLM	330MHz ~ 660MHz
PLLD	330MHz ~ 660MHz
KM4/KR4	≤300MHz	0.9V
KM4/KR4	≤400MHz	1.0V

SoC & PSRAM Clock Set Flow

(Optional) Find out the speed limit of embedded PSRAM device, if not sure.
1. Refer to the BOOT_ChipInfo_PSRAMType() function in the bootloaderbootloader_km4.c file, and print the value of PSRAM_CLK_LIMIT_GET(ChipInfo_PSRAMType()). This can be used to read the speed limit of the built-in PSRAM from the OTP.
2. Refer to the chip’s specification document to understand the speed limits of the built-in PSRAM.

Check the value of Boot_SocClk_Info_Idx and the clock info in ameba_bootcfg.c.

// for kr4/km4, max 400MHz under 1.0v, max 200MHz under 0.9v
// for dsp, max 500MHz under 1.0v, max 400MHz under 0.9v
// CPUPLL(PLLM)/DSPPLL(PLLD) can be 330MHz~660MHz
// All CLKDIV range is [1, 16]
SocClk_Info_TypeDef SocClk_Info[] = {
   /* PLLM_CLK,  PLLD_CLK,  Vol_Type,      CPU_CKD,             PSRAMC_CKD */
   {PLL_600M,    PLL_500M,  CORE_VOL_0P9,  CLKDIV(3) | ISPLLM,  CLKDIV(2) | ISPLLM}, /* 0.9V, PSRAM-166M */
   {PLL_600M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(3) | ISPLLM,  CLKDIV(2) | ISPLLM}, /* 1.0V, PSRAM-166M */
   {PLL_400M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(2) | ISPLLM,  CLKDIV(1) | ISPLLM}, /* 1.0V, PSRAM-200M */
   {PLL_480M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(2) | ISPLLM,  CLKDIV(1) | ISPLLD}, /* 1.0V, PSRAM-250M */
};

/**
* @brif  SocClk_Info select
* Boot_SocClk_Info_Idx valid value is [0, 3] and 0xFF
* when Boot_SocClk_Info_Idx is 0xFF, set socclk by chipinfo Automatically
* when Boot_SocClk_Info_Idx is [0, 3], set socclk by SocClk_Info[Boot_SocClk_Info_Idx]
*/
u8 Boot_SocClk_Info_Idx = 0xFF;

If Boot_SocClk_Info_Idx is 0xFF (default), the bootloader will set the SoC clock automatically according to the embedded PSRAM type.
If Boot_SocClk_Info_Idx is not 0xFF, the bootloader will set the SoC clock defined by SocClk_Info[Boot_SocClk_Info_Idx].

For example, if Boot_SocClk_Info_Idx is 0, and the maximum operating frequency of PSRAM is 166MHz, the bootloader will use SocClk_Info[0] for configuration. This means the clock frequency of KM4/KR4 will be set to 1/3 of the PLLM frequency, and the PSRAMC (twice the PSRAM clock) rate will be set to 1/2 of the PLLM frequency. The clock rates for the remaining modules will be automatically set by the software to reasonable values based on their maximum operating speeds.

PSRAM type	PSRAM speed	SocClk_Info[x]	Clock Info
No PSRAM		SocClk_Info[0]	PLLM: 600MHz PLLD: 500MHz KM4/KR4: PLLM/3
With PSRAM	≤166MHz	SocClk_Info[1]	PLLM: 600MHz PLLD: 500MHz KM4/KR4: PLLM/3 PSRAMC: PLLM/2
With PSRAM	≤200MHz	SocClk_Info[2]	PLLM: 400MHz PLLD: 500MHz KM4/KR4: PLLM/2 PSRAMC: PLLM

Refer to one of the following methods to change the SoC clock if needed.
- Keep the Boot_SocClk_Info_Idx 0xFF, and only change the clock info of SocClk_Info[x] to set the clocks of PLLM/PLLD and CPUs.
- Modify the Boot_SocClk_Info_Idx to [0, sizeof(SocClk_Info)], and then customize the clock configuration information in SocClk_Info[Boot_SocClk_Info_Idx].
Note
- Consider the limitations of the hardware and do not set the clock info illogically.
- The PLLD can be disabled if you do not need it work.
Re-build the project and download the new image again.

Boot_Agg_En

The Boot_Agg_En is used with Trace Tool to sort out boot logs from different cores. It can be enabled through Boot_Agg_En.

/**
* @brif  Loguart AGG enable or disable
*    FALSE: disable
*    TRUE: enable
*/
u8 Boot_Agg_En = FALSE;

Note

Refer to Chapter Trace Tool for more information.

github source code

ameba_bootcfg.c

The KM4 boots at 150MHz at the BootROM Stage, and switches to a higher frequency during the bootloader Stage.

There are some limitations when changing the SoC clock:

Clock	Frequency	Core voltage	Note
PLLM	330MHz ~ 660MHz
PLLD	330MHz ~ 660MHz		Can not exceed the maximum frequency of DSP clock
KM4/KR4	≤300MHz	0.9V
KM4/KR4	≤400MHz	1.0V
DSP	≤400MHz	0.9V	The same as PLLD
DSP	≤500MHz	1.0V	The same as PLLD

SoC & PSRAM Clock Set Flow

(Optional) Find out the speed limit of embedded PSRAM device, if not sure.
1. Refer to the BOOT_ChipInfo_PSRAMType() function in the bootloaderbootloader_km4.c file, and print the value of PSRAM_CLK_LIMIT_GET(ChipInfo_PSRAMType()). This can be used to read the speed limit of the built-in PSRAM from the OTP.
2. Refer to the chip’s specification document to understand the speed limits of the built-in PSRAM.

Check the value of Boot_SocClk_Info_Idx and the clock info in ameba_bootcfg.c.

// for kr4/km4, max 400MHz under 1.0v, max 200MHz under 0.9v
// for dsp, max 500MHz under 1.0v, max 400MHz under 0.9v
// CPUPLL(PLLM)/DSPPLL(PLLD) can be 330MHz~660MHz
// All CLKDIV range is [1, 16]
SocClk_Info_TypeDef SocClk_Info[] = {
   /* PLLM_CLK,  PLLD_CLK,  Vol_Type,      CPU_CKD,             PSRAMC_CKD */
   {PLL_600M,    PLL_500M,  CORE_VOL_0P9,  CLKDIV(3) | ISPLLM,  CLKDIV(2) | ISPLLM}, /* 0.9V, PSRAM-166M */
   {PLL_600M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(3) | ISPLLM,  CLKDIV(2) | ISPLLM}, /* 1.0V, PSRAM-166M */
   {PLL_400M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(2) | ISPLLM,  CLKDIV(1) | ISPLLM}, /* 1.0V, PSRAM-200M */
   {PLL_480M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(2) | ISPLLM,  CLKDIV(1) | ISPLLD}, /* 1.0V, PSRAM-250M */
};

/**
* @brif  SocClk_Info select
* Boot_SocClk_Info_Idx valid value is [0, 3] and 0xFF
* when Boot_SocClk_Info_Idx is 0xFF, set socclk by chipinfo Automatically
* when Boot_SocClk_Info_Idx is [0, 3], set socclk by SocClk_Info[Boot_SocClk_Info_Idx]
*/
u8 Boot_SocClk_Info_Idx = 0xFF;

If Boot_SocClk_Info_Idx is 0xFF (default), the bootloader will set the SoC clock automatically according to the embedded PSRAM type.
If Boot_SocClk_Info_Idx is not 0xFF, the bootloader will set the SoC clock defined by SocClk_Info[Boot_SocClk_Info_Idx].

For example, if Boot_SocClk_Info_Idx is 0, and the maximum operating frequency of PSRAM is 166MHz, the bootloader will use SocClk_Info[0] for configuration. This means the clock frequency of KM4/KR4 will be set to 1/3 of the PLLM frequency, and the PSRAMC (twice the PSRAM clock) rate will be set to 1/2 of the PLLM frequency. The clock rates for the remaining modules will be automatically set by the software to reasonable values based on their maximum operating speeds.

PSRAM type	PSRAM speed	SocClk_Info[x]	Clock Info
With PSRAM	≤250MHz	SocClk_Info[3]	PLLM: 480MHz PLLD: 500MHz KM4/KR4: PLLM/2 PSRAMC: PLLD DSP: PLLD

Refer to one of the following methods to change the SoC clock if needed.
- Keep the Boot_SocClk_Info_Idx 0xFF, and only change the clock info of SocClk_Info[x] to set the clocks of PLLM/PLLD and CPUs.
- Modify the Boot_SocClk_Info_Idx to [0, sizeof(SocClk_Info)], and then customize the clock configuration information in SocClk_Info[Boot_SocClk_Info_Idx].
Note

Consider the limitations of the hardware and do not set the clock info illogically.
Re-build the project and download the new image again.

Boot_Agg_En

The Boot_Agg_En is used with Trace Tool to sort out boot logs from different cores. It can be enabled through Boot_Agg_En.

/**
* @brif  Loguart AGG enable or disable
*    FALSE: disable
*    TRUE: enable
*/
u8 Boot_Agg_En = FALSE;

Note

Refer to Chapter Trace Tool for more information.

github source code

ameba_bootcfg.c

The KM4 boots at 150MHz at the BootROM Stage, and switches to a higher frequency during the bootloader Stage.

There are some limitations when changing the SoC clock:

Clock	Frequency	Core voltage	Note
PLLM	330MHz ~ 660MHz
PLLD	330MHz ~ 660MHz		Can not exceed the maximum frequency of DSP clock
KM4/KR4	≤300MHz	0.9V
KM4/KR4	≤400MHz	1.0V
DSP	≤400MHz	0.9V	The same as PLLD
DSP	≤500MHz	1.0V	The same as PLLD

SoC & PSRAM Clock Set Flow

(Optional) Find out the speed limit of embedded PSRAM device, if not sure.
1. Refer to the BOOT_ChipInfo_PSRAMType() function in the bootloaderbootloader_km4.c file, and print the value of PSRAM_CLK_LIMIT_GET(ChipInfo_PSRAMType()). This can be used to read the speed limit of the built-in PSRAM from the OTP.
2. Refer to the chip’s specification document to understand the speed limits of the built-in PSRAM.

Check the value of Boot_SocClk_Info_Idx and the clock info in ameba_bootcfg.c.

// for kr4/km4, max 400MHz under 1.0v, max 200MHz under 0.9v
// for dsp, max 500MHz under 1.0v, max 400MHz under 0.9v
// CPUPLL(PLLM)/DSPPLL(PLLD) can be 330MHz~660MHz
// All CLKDIV range is [1, 16]
SocClk_Info_TypeDef SocClk_Info[] = {
   /* PLLM_CLK,  PLLD_CLK,  Vol_Type,      CPU_CKD,             PSRAMC_CKD */
   {PLL_600M,    PLL_500M,  CORE_VOL_0P9,  CLKDIV(3) | ISPLLM,  CLKDIV(2) | ISPLLM}, /* 0.9V, PSRAM-166M */
   {PLL_600M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(3) | ISPLLM,  CLKDIV(2) | ISPLLM}, /* 1.0V, PSRAM-166M */
   {PLL_400M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(2) | ISPLLM,  CLKDIV(1) | ISPLLM}, /* 1.0V, PSRAM-200M */
   {PLL_480M,    PLL_500M,  CORE_VOL_1P0,  CLKDIV(2) | ISPLLM,  CLKDIV(1) | ISPLLD}, /* 1.0V, PSRAM-250M */
};

/**
* @brif  SocClk_Info select
* Boot_SocClk_Info_Idx valid value is [0, 3] and 0xFF
* when Boot_SocClk_Info_Idx is 0xFF, set socclk by chipinfo Automatically
* when Boot_SocClk_Info_Idx is [0, 3], set socclk by SocClk_Info[Boot_SocClk_Info_Idx]
*/
u8 Boot_SocClk_Info_Idx = 0xFF;

If Boot_SocClk_Info_Idx is 0xFF (default), the bootloader will set the SoC clock automatically according to the embedded PSRAM type.
If Boot_SocClk_Info_Idx is not 0xFF, the bootloader will set the SoC clock defined by SocClk_Info[Boot_SocClk_Info_Idx].

For example, if Boot_SocClk_Info_Idx is 0, and the maximum operating frequency of PSRAM is 166MHz, the bootloader will use SocClk_Info[0] for configuration. This means the clock frequency of KM4/KR4 will be set to 1/3 of the PLLM frequency, and the PSRAMC (twice the PSRAM clock) rate will be set to 1/2 of the PLLM frequency. The clock rates for the remaining modules will be automatically set by the software to reasonable values based on their maximum operating speeds.

PSRAM type	PSRAM speed	SocClk_Info[x]	Clock Info
With PSRAM	≤250MHz	SocClk_Info[3]	PLLM: 480MHz PLLD: 500MHz KM4/KR4: PLLM/2 PSRAMC: PLLD DSP: PLLD

Refer to one of the following methods to change the SoC clock if needed.
- Keep the Boot_SocClk_Info_Idx 0xFF, and only change the clock info of SocClk_Info[x] to set the clocks of PLLM/PLLD and CPUs.
- Modify the Boot_SocClk_Info_Idx to [0, sizeof(SocClk_Info)], and then customize the clock configuration information in SocClk_Info[Boot_SocClk_Info_Idx].
Note

Consider the limitations of the hardware and do not set the clock info illogically.
Re-build the project and download the new image again.

Boot_Agg_En

The Boot_Agg_En is used with Trace Tool to sort out boot logs from different cores. It can be enabled through Boot_Agg_En.

/**
* @brif  Loguart AGG enable or disable
*    FALSE: disable
*    TRUE: enable
*/
u8 Boot_Agg_En = FALSE;

Note

Refer to Chapter Trace Tool for more information.

github source code

ameba_bootcfg.c

The KM4 boots at 200MHz at the BootRom Stage, and switches to a higher frequency during the bootloader Stage.

There are some limitations when changing the SoC clock:

Clock	Frequency	Core voltage	Note
NPPLL	800MHz ~ 1.0GHz
APPLL	1.0GHz ~ 1.6GHz		Can not exceed the maximum frequency of CA32 clock
KM4	≤250MHz	0.9V
KM4	≤333MHz	1.0V
CA32	≤920MHz	0.9V
CA32	≤1200MHz	1.0V	When the Memory Type is DDR, the limit is 1320MHz.

SoC & PSRAM 时钟设置流程

Check the value of SocClk_Info[] in ameba_bootcfg.c.

// for km4, max 333MHz under 1.0v, max 250MHz under 0.9v
// for AP, max 1200MHz under 1.0v, max 920MHz under 0.9v
// NP PLL can be 800MHz~1000MHz
SocClk_Info_TypeDef SocClk_Info[1] = {
   /* NPPLL_CLK,   APPLL_Clk,    Vol_Type,  KM4_CPU_CKD,  AP_CPU_CKD */
   {NPPLL_1000M,   APPLL_1200M,  VOL_10,    CLKDIV(3),    CLKDIV(1) | ISAPPLL}, //best porformance
   // {NPPLL_920M, APPLL_NULL,   VOL_09,    CLKDIV(4),    CLKDIV(1) | ISNPPLL},
};

The Bootloader will configure the SoC voltage and clock according to the definition in SocClk_Info[0]. The clock settings for the remaining modules will be automatically set to reasonable values by the software based on their maximum operating speeds.
- KM4 Clock: NPPLL / SocClk_Info[0].KM4_CPU_CKD
- CA32 Clock: If SocClk_Info[0].AP_CPU_CKD is ISAPPLL, then CA32 Clock = APPLL / SocClk_Info[0].AP_CPU_CKD, otherwise CA32 Clock = NPPLL / SocClk_Info[0].AP_CPU_CKD
If necessary, customize the clock configuration information in SocClk_Info.

Note

Please consider the hardware limitations carefully to avoid setting illegal clock configuration parameters.
Recompile the project and download the new firmware.

Boot_Agg_En

The Boot_Agg_En is used with Trace Tool to sort out boot logs from different cores. It can be enabled through Boot_Agg_En.

/**
* @brif  Loguart AGG enable or disable
*    FALSE: disable
*    TRUE: enable
*/
u8 Boot_Agg_En = FALSE;

Note

Refer to Chapter Trace Tool for more information.

github source code

ameba_bootcfg.c

The KM4_TZ boots at 200MHz at the BootRom Stage, and switches to a higher frequency during the bootloader Stage.

There are some limitations when changing the SoC clock:

Clock	Frequency	Core voltage
SYSPLL	600MHz ~ 1.0GHz
USBPLL	≤500MHz
CPU	≤266.7MHz	0.9V
CPU	≤333.34MHz	1.0V

SoC Clock Set Flow

Check the value of SocClk_Info[] in ameba_bootcfg.c.

SocClk_Info_TypeDef SocClk_Info[1] = {
   /* USBPLL_CLK,         SYSPLL_CLK,             Vol_Type,               CPU_CKD*/
#if defined CLKCFG_0P9_NO_SYSPLL
   /* 1. Low power consumption scenario. (CPU clk: 240Mhz) */
   {PLL_960M,                     PLL_NONE,               CORE_VOL_0P9,   CLKDIV(4) | IS_USB_PLL},
#elif defined CLKCFG_0P9_RMII_USB
   /* 2. Use RMII or/and USB peripherals. (CPU clk: 240Mhz) */
   {PLL_960M,                     PLL_400M,               CORE_VOL_0P9,   CLKDIV(4) | IS_USB_PLL},
#elif defined CLKCFG_0P9_AUDIO98P304M_USB
   /* 3. Use Audio or/and USB peripherals. (CPU clk: 240Mhz) */
   {PLL_960M,                     PLL_393P216M,   CORE_VOL_0P9,   CLKDIV(4) | IS_USB_PLL},
#elif defined CLKCFG_0P9_AUDIO45P1584M_USB
   /* 4. Use Audio or/and RMII peripherals. (CPU clk: 240Mhz) */
   {PLL_960M,                     PLL_361P2672M,  CORE_VOL_0P9,   CLKDIV(4) | IS_USB_PLL},
#elif defined CLKCFG_0P9_AUDIO_RMII
   /* 5. Use Audio or/and RMII peripherals. (CPU clk: 266.7Mhz) */
   {PLL_800M,                     PLL_393P216M,   CORE_VOL_0P9,   CLKDIV(3) | IS_USB_PLL},
#elif defined CLKCFG_1P0_RMII_USB
   /* 6. 1P0_RMII_USB: Use RMII or/and USB peripherals. (CPU clk: 320Mhz) */
   {PLL_960M,                     PLL_400M,               CORE_VOL_1P0,   CLKDIV(3) | IS_USB_PLL},
#elif defined CLKCFG_1P0_AUDIO_USB
   /* 7. 1P0_AUDIO_USB: Use Audio or/and USB peripherals. (CPU clk: 320Mhz) */
   {PLL_960M,                     PLL_393P216M,   CORE_VOL_1P0,   CLKDIV(3) | IS_USB_PLL},
#elif defined CLKCFG_1P0_AUDIO_RMII
   /* 8. 1P0_AUDIO_RMII: Use Audio or/and RMII peripherals. (CPU clk: 333.3Mhz) */
   {PLL_1000M,                    PLL_393P216M,   CORE_VOL_1P0,   CLKDIV(3) | IS_USB_PLL},
#else
#error "Incorrect clock config"
#endif
};

The Bootloader will configure the SoC voltage and clock according to the definition in SocClk_Info[0]. The clock settings for the remaining modules will be automatically set to reasonable values by the software based on their maximum operating speeds.
- CPU Clock: If SocClk_Info[0].CPU_CKD is IS_USB_PLL, then CPU Clock = USBPLL / SocClk_Info[0].CPU_CKD, otherwise CPU Clock = SYSPLL / SocClk_Info[0].CPU_CKD
If necessary, customize the clock configuration information in SocClk_Info.
Note
- Please consider the hardware limitations carefully to avoid setting illegal clock configuration parameters.
- The USBPLL or SYSPLL can be disabled if you do not need it work.
Recompile the project and download the new firmware.

Boot_Agg_En

The Boot_Agg_En is used with Trace Tool to sort out boot logs from different cores. It can be enabled through Boot_Agg_En.

/**
* @brif  Loguart AGG enable or disable
*    FALSE: disable
*    TRUE: enable
*/
u8 Boot_Agg_En = FALSE;

Note

Refer to Chapter Trace Tool for more information.

ameba_flashcfg

This section introduces the Flash-related configurations including speed, read mode, layout and protect mode.

github source code

ameba_flashcfg.c

Flash_Speed

The frequency of the SPIC controller is set to XTAL (40MHz) during the BootRom stage, and switches to a higher frequency during the Bootloader stage. The Flash runs at half the speed of the SPIC controller. By default, the SPIC controller’s speed is derived from the PLL divider, but it must remain below SPIC_CLK_LIMIT (208MHz).

If the Flash needs to run slower, modify the value of Flash_Speed (for SPIC0) or Data_Flash_Speed (for SPIC1), which is the PLL division factor.

const u16 Flash_Speed = CLKDIV(2);
const u16 Data_Flash_Speed = CLKDIV(2);

Note

Refer to ameba_bootcfg for details about the Frequency of PLL.
The maximum clock of Flash is SPIC_CLK_LIMIT/2. The initial flow will automatically check whether the configured speed is higher than the maximun one or not.
Flash has already been set to optimal performance during initialization, so it is not recommended to modify Flash_Speed and Flash_ReadMode, or Data_Flash_Speed and Data_Flash_ReadMode.

Flash_ReadMode

During the BootRom stage, the SPIC operates in 1IO mode, and switches to the mode specified by Flash_ReadMode (default is 4IO) during the Bootloader stage. If the currently configured read mode is not supported, the system will automatically try other modes until a compatible mode is found.

Flash_Layout

The default Flash layout in the SDK are illustrated in Chapter Flash Layout. If you want to modify the Flash layout, refer to Section Flash Layout Modification Guide.

Flash Protect Enable

For more information about this function, refer to Section Flash Protection Mechanism .

github source code

ameba_flashcfg.c

Flash_Speed

The frequency of the SPIC controller is set to XTAL (40MHz) during the BootRom stage, and switches to a higher frequency during the Bootloader stage. The Flash runs at half the speed of the SPIC controller. By default, the SPIC controller’s speed is derived from the PLLM divider, but it must remain below SPIC_CLK_LIMIT (208MHz).

If the Flash needs to run slower, change the value of Flash_Speed, which is the PLLM division factor.

const u16 Flash_Speed = 0xFF;

Note

Refer to ameba_bootcfg for details about the Frequency of PLLM.
The maximum clock of Flash is SPIC_CLK_LIMIT/2. The initial flow will automatically check whether the configured speed is higher than the maximun one or not.

Flash_ReadMode

During the BootRom stage, the SPIC operates in 1IO mode, and switches to the mode specified by Flash_ReadMode (default is 4IO) during the Bootloader stage. If the currently configured read mode is not supported, the system will automatically try other modes until a compatible mode is found.

Flash_Layout

The default Flash layout in the SDK are illustrated in Chapter Flash Layout. If you want to modify the Flash layout, refer to Section Flash Layout Modification Guide.

Flash Protect Enable

For more information about this function, refer to Section Flash Protection Mechanism .

github source code

ameba_flashcfg.c

Flash_Speed

The frequency of the SPIC controller is set to XTAL (40MHz) during the BootRom stage, and switches to a higher frequency during the Bootloader stage. The Flash runs at half the speed of the SPIC controller. By default, the SPIC controller’s speed is derived from the PLLM divider, but it must remain below SPIC_CLK_LIMIT (208MHz).

If the Flash needs to run slower, change the value of Flash_Speed, which is the PLLM division factor.

const u16 Flash_Speed = 0xFF;

Note

Refer to ameba_bootcfg for details about the Frequency of PLLM.
The maximum clock of Flash is SPIC_CLK_LIMIT/2. The initial flow will automatically check whether the configured speed is higher than the maximun one or not.

Flash_ReadMode

During the BootRom stage, the SPIC operates in 1IO mode, and switches to the mode specified by Flash_ReadMode (default is 4IO) during the Bootloader stage. If the currently configured read mode is not supported, the system will automatically try other modes until a compatible mode is found.

Flash_Layout

The default Flash layout in the SDK are illustrated in Chapter Flash Layout. If you want to modify the Flash layout, refer to Section Flash Layout Modification Guide.

Flash Protect Enable

For more information about this function, refer to Section Flash Protection Mechanism .

github source code

ameba_flashcfg.c

Flash_Speed

The frequency of the SPIC controller is set to XTAL (40MHz) during the BootRom stage, and switches to a higher frequency during the Bootloader stage. The Flash runs at half the speed of the SPIC controller. By default, the SPIC controller’s speed is derived from the PLLM divider, but it must remain below SPIC_CLK_LIMIT (208MHz).

If the Flash needs to run slower, change the value of Flash_Speed, which is the PLLM division factor.

const u16 Flash_Speed = 0xFF;

Note

Refer to ameba_bootcfg for details about the Frequency of PLLM.
The maximum clock of Flash is SPIC_CLK_LIMIT/2. The initial flow will automatically check whether the configured speed is higher than the maximun one or not.

Flash_ReadMode

During the BootRom stage, the SPIC operates in 1IO mode, and switches to the mode specified by Flash_ReadMode (default is 4IO) during the Bootloader stage. If the currently configured read mode is not supported, the system will automatically try other modes until a compatible mode is found.

Flash_Layout

The default Flash layout in the SDK are illustrated in Chapter Flash Layout. If you want to modify the Flash layout, refer to Section Flash Layout Modification Guide.

Flash Protect Enable

For more information about this function, refer to Section Flash Protection Mechanism .

github source code

ameba_flashcfg.c

Flash_Speed

The frequency of the SPIC controller is set to XTAL (40MHz) during the BootRom stage, and switches to a higher frequency during the Bootloader stage. The Flash runs at half the speed of the SPIC controller. By default, the SPIC controller’s speed is derived from the NPPLL divider, but it must remain below SPIC_CLK_LIMIT (208MHz).

If the Flash needs to run slower, change the value of Flash_Speed, which is the NPPLL division factor.

const u16 Flash_Speed = 0x7FF;

Note

Refer to ameba_bootcfg for details about the Frequency of NPPLL.
The maximum clock of Flash is SPIC_CLK_LIMIT/2. The initial flow will automatically check whether the configured speed is higher than the maximun one or not.

Flash_ReadMode

During the BootRom stage, the SPIC operates in 1IO mode, and switches to the mode specified by Flash_ReadMode (default is 4IO) during the Bootloader stage. If the currently configured read mode is not supported, the system will automatically try other modes until a compatible mode is found.

Flash_Layout

The default Flash layout in the SDK are illustrated in Chapter Flash Layout. If you want to modify the Flash layout, refer to Section Flash Layout Modification Guide.

Flash Protect Enable

For more information about this function, refer to Section Flash Protection Mechanism .

github source code

ameba_flashcfg.c

Flash_Speed

The frequency of the SPIC controller is set to XTAL (40MHz) during the BootRom stage, and switches to a higher frequency during the Bootloader stage. The Flash runs at half the speed of the SPIC controller. By default, the SPIC controller’s speed is derived from the PLL divider, but it must remain below SPIC_CLK_LIMIT (208MHz).

Note

The maximum clock of Flash is SPIC_CLK_LIMIT/2. The initial flow will automatically check whether the configured speed is higher than the maximun one or not.
Flash has already been set to optimal performance during initialization, so it is not recommended to modify Flash_Speed and Flash_ReadMode, or Data_Flash_Speed and Data_Flash_ReadMode.

Flash_ReadMode

During the BootRom stage, the SPIC operates in 1IO mode, and switches to the mode specified by Flash_ReadMode (default is 4IO) during the Bootloader stage. If the currently configured read mode is not supported, the system will automatically try other modes until a compatible mode is found.

Flash_Layout

The default Flash layout in the SDK are illustrated in Chapter Flash Layout. If you want to modify the Flash layout, refer to Section Flash Layout Modification Guide.

Flash Protect Enable

For more information about this function, refer to Section Flash Protection Mechanism .

ameba_boot_trustzonecfg

This section introduces TrustZone-related configurations, focusing primarily on the configuration of the MPC and SAU in chips that support Secure features. If the chip does not support the Secure feature, this configuration profile will be ignored.

github source code

ameba_boot_trustzonecfg.c

sau_config

Users can configure the security attributes of KM4 by modifying the values in sau_config. Within the specified interval [Start, End], users can set NSC to 0 or 1 to designate whether the area is non-secure.

If NSC is set to 1, the area will be treated as secure code, i.e., Non-secure Callable (NSC);
If NSC is set to 0, the area will be treated as non-secure code, and Non-secure KM4 will be able to access this area.
Areas that are not set will be treated as secure code, accessible by Secure KM4.

mpc1_config

Users can configure the security attributes of certain SRAM intervals by modifying the values in mpc1_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc2_config

Users can configure the security attributes of certain PSRAM intervals by modifying the values in mpc2_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

Note

If the chip supports the Secure Image Protection (RDP) feature, this file will be compiled and linked into the Bootloader; if the chip does not support the Secure Image Protection (RDP) feature, this file will be ignored.
You can refer to TrustZone 安全区域大小调整方法 to modify ameba_boot_trustzonecfg.c.

github source code

ameba_boot_trustzonecfg.c

sau_config

Users can configure the security attributes of KM4 by modifying the values in sau_config. Within the specified interval [Start, End], users can set NSC to 0 or 1 to designate whether the area is non-secure.

If NSC is set to 1, the area will be treated as secure code, i.e., Non-secure Callable (NSC);
If NSC is set to 0, the area will be treated as non-secure code, and Non-secure KM4 will be able to access this area.
Areas that are not set will be treated as secure code, accessible by Secure KM4.

mpc1_config

Users can configure the security attributes of certain hs_sram0(0x20000000~0x20040000) intervals by modifying the values in mpc1_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc2_config

Users can configure the security attributes of certain hs_sram1(0x20040000~0x20080000) intervals by modifying the values in mpc2_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc3_config

Users can configure the security attributes of certain PSRAM intervals by modifying the values in mpc3_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

Note

If the chip supports the Secure Image Protection (RDP) feature, this file will be compiled and linked into the Bootloader; if the chip does not support the Secure Image Protection (RDP) feature, this file will be ignored.
You can refer to TrustZone 安全区域大小调整方法 to modify ameba_boot_trustzonecfg.c.

github source code

ameba_boot_trustzonecfg.c

sau_config

Users can configure the security attributes of KM4 by modifying the values in sau_config. Within the specified interval [Start, End], users can set NSC to 0 or 1 to designate whether the area is non-secure.

If NSC is set to 1, the area will be treated as secure code, i.e., Non-secure Callable (NSC);
If NSC is set to 0, the area will be treated as non-secure code, and Non-secure KM4 will be able to access this area.
Areas that are not set will be treated as secure code, accessible by Secure KM4.

mpc1_config

Users can configure the security attributes of certain hs_sram0(0x20000000~0x20040000) intervals by modifying the values in mpc1_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc2_config

Users can configure the security attributes of certain hs_sram1(0x20040000~0x20080000) intervals by modifying the values in mpc2_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc3_config

Users can configure the security attributes of certain PSRAM intervals by modifying the values in mpc3_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

Note

If the chip supports the Secure Image Protection (RDP) feature, this file will be compiled and linked into the Bootloader; if the chip does not support the Secure Image Protection (RDP) feature, this file will be ignored.
You can refer to TrustZone 安全区域大小调整方法 to modify ameba_boot_trustzonecfg.c.

github source code

ameba_boot_trustzonecfg.c

sau_config

Users can configure the security attributes of KM4 by modifying the values in sau_config. Within the specified interval [Start, End], users can set NSC to 0 or 1 to designate whether the area is non-secure.

If NSC is set to 1, the area will be treated as secure code, i.e., Non-secure Callable (NSC);
If NSC is set to 0, the area will be treated as non-secure code, and Non-secure KM4 will be able to access this area.
Areas that are not set will be treated as secure code, accessible by Secure KM4.

mpc1_config

Users can configure the security attributes of certain hs_sram0(0x20000000~0x20040000) intervals by modifying the values in mpc1_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc2_config

Users can configure the security attributes of certain hs_sram1(0x20040000~0x20080000) intervals by modifying the values in mpc2_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc3_config

Users can configure the security attributes of certain PSRAM intervals by modifying the values in mpc3_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

Note

If the chip supports the Secure Image Protection (RDP) feature, this file will be compiled and linked into the Bootloader; if the chip does not support the Secure Image Protection (RDP) feature, this file will be ignored.
You can refer to TrustZone 安全区域大小调整方法 to modify ameba_boot_trustzonecfg.c.

github source code

ameba_boot_trustzonecfg.c

sau_config

Users can configure the security attributes of KM4 by modifying the values in sau_config. Within the specified interval [Start, End], users can set NSC to 0 or 1 to designate whether the area is non-secure.

If NSC is set to 1, the area will be treated as secure code, i.e., Non-secure Callable (NSC);
If NSC is set to 0, the area will be treated as non-secure code, and Non-secure KM4 will be able to access this area.
Areas that are not set will be treated as secure code, accessible by Secure KM4.

mpc1_config

Users can configure the security attributes of certain HS_SRAM intervals by modifying the values in mpc1_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc2_config

Users can configure the security attributes of certain PSRAM/DRAM intervals by modifying the values in mpc2_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

Note

If the chip supports the Secure Image Protection (RDP) feature, this file will be compiled and linked into the Bootloader; if the chip does not support the Secure Image Protection (RDP) feature, this file will be ignored.
You can refer to TrustZone 安全区域大小调整方法 to modify ameba_boot_trustzonecfg.c.

github source code

ameba_boot_trustzonecfg.c

sau_config

Users can configure the security attributes of KM4 by modifying the values in sau_config. Within the specified interval [Start, End], users can set NSC to 0 or 1 to designate whether the area is non-secure.

If NSC is set to 1, the area will be treated as secure code, i.e., Non-secure Callable (NSC);
If NSC is set to 0, the area will be treated as non-secure code, and Non-secure KM4 will be able to access this area.
Areas that are not set will be treated as secure code, accessible by Secure KM4.

mpc1_config

Users can configure the security attributes of certain Flash intervals by modifying the values in mpc1_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc2_config

Users can configure the security attributes of certain SRAM intervals by modifying the values in mpc2_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

mpc3_config

Users can configure the security attributes of certain PSRAM intervals by modifying the values in mpc3_config:

Within the specified interval [Start, End], Non-secure Master can access this area;
Areas that are not set can only be accessed by Secure Master.

ameba_intfcfg

This section introduces peripheral pin assignment, which refers to mapping the physical pins of the chip to various peripheral functions.

github source code

ameba_intfcfg.c

sdio_config

sdio_config is mainly used to configure the relevant interfaces of the SDIO Device, refer to Section :ref:`sdio_config`.

github source code

ameba_intfcfg.c

sdioh_config

sdioh_config is mainly used to configure the relevant interfaces of the SDIO Host, refer to Section :ref:`sdioh_config`.

github source code

ameba_intfcfg.c

sdio_config

sdio_config is mainly used to configure the relevant interfaces of the SDIO Device, refer to Section :ref:`sdio_config`.

ameba_pinmapcfg

This section introduces the pull-up and pull-down status of each pin configged by pinmap_init() during the initialization phase.

github source code

ameba_pinmapcfg.c

pmap_func

The pmap_func array is mainly used to configure the pull-up and pull-down status of each pin:

The Func PU/PD controls the default pull-up and pull-down states of pins when the SOC is Active. In main() or subsequent tasks, the pull-up and pull-down states of pins need to be set according to the specific IP requirements when the SOC is Active.
The Slp PU/PD controls the pull-up and pull-down states when the SOC is in Sleep mode. If not set correctly, leakage current may occur on that pin during sleep, Please modify according to the hardware status.

const PMAP_TypeDef pmap_func[] = {
     //Pin Name              Func PU/PD                              Slp PU/PD
     {_PA_0,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_1,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_2,                 GPIO_PuPd_KEEP,         GPIO_PuPd_UP},
   ...
};

github source code

ameba_pinmapcfg.c

pmap_func

The pmap_func array is mainly used to configure the pull-up and pull-down status of each pin:

The Func PU/PD controls the default pull-up and pull-down states of pins when the SOC is Active. In main() or subsequent tasks, the pull-up and pull-down states of pins need to be set according to the specific IP requirements when the SOC is Active.
The Slp PU/PD controls the pull-up and pull-down states when the SOC is in Sleep mode. If not set correctly, leakage current may occur on that pin during sleep, Please modify according to the hardware status.

const PMAP_TypeDef pmap_func[] = {
     //Pin Name              Func PU/PD                              Slp PU/PD
     {_PA_0,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_1,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_2,                 GPIO_PuPd_KEEP,         GPIO_PuPd_UP},
   ...
};

github source code

ameba_pinmapcfg.c

pmap_func

The pmap_func array is mainly used to configure the pull-up and pull-down status of each pin:

The Func PU/PD controls the default pull-up and pull-down states of pins when the SOC is Active. In main() or subsequent tasks, the pull-up and pull-down states of pins need to be set according to the specific IP requirements when the SOC is Active.
The Slp PU/PD controls the pull-up and pull-down states when the SOC is in Sleep mode. If not set correctly, leakage current may occur on that pin during sleep, Please modify according to the hardware status.

const PMAP_TypeDef pmap_func[] = {
     //Pin Name              Func PU/PD                              Slp PU/PD
     {_PA_0,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_1,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_2,                 GPIO_PuPd_KEEP,         GPIO_PuPd_UP},
   ...
};

github source code

ameba_pinmapcfg.c

pmap_func

The pmap_func array is mainly used to configure the pull-up and pull-down status of each pin:

The Func PU/PD controls the default pull-up and pull-down states of pins when the SOC is Active. In main() or subsequent tasks, the pull-up and pull-down states of pins need to be set according to the specific IP requirements when the SOC is Active.
The Slp PU/PD controls the pull-up and pull-down states when the SOC is in Sleep mode. If not set correctly, leakage current may occur on that pin during sleep, Please modify according to the hardware status.

const PMAP_TypeDef pmap_func[] = {
     //Pin Name              Func PU/PD                              Slp PU/PD
     {_PA_0,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_1,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_2,                 GPIO_PuPd_KEEP,         GPIO_PuPd_UP},
   ...
};

github source code

ameba_pinmapcfg.c

pmap_func

The pmap_func array is mainly used to configure the pull-up and pull-down status of each pin:

The Func PU/PD controls the default pull-up and pull-down states of pins when the SOC is Active. In main() or subsequent tasks, the pull-up and pull-down states of pins need to be set according to the specific IP requirements when the SOC is Active.
The Slp PU/PD controls the pull-up and pull-down states when the SOC is in Sleep mode. If not set correctly, leakage current may occur on that pin during sleep, Please modify according to the hardware status.

const PMAP_TypeDef pmap_func[] = {
     //Pin Name              Func PU/PD                              Slp PU/PD
     {_PA_0,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_1,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_2,                 GPIO_PuPd_KEEP,         GPIO_PuPd_UP},
   ...
};

github source code

ameba_pinmapcfg.c

pmap_func

The pmap_func array is mainly used to configure the pull-up and pull-down status of each pin:

The Func PU/PD controls the default pull-up and pull-down states of pins when the SOC is Active. In main() or subsequent tasks, the pull-up and pull-down states of pins need to be set according to the specific IP requirements when the SOC is Active.
The Slp PU/PD controls the pull-up and pull-down states when the SOC is in Sleep mode. If not set correctly, leakage current may occur on that pin during sleep, Please modify according to the hardware status.

const PMAP_TypeDef pmap_func[] = {
     //Pin Name              Func PU/PD                              Slp PU/PD
     {_PA_0,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_1,                 GPIO_PuPd_UP,                   GPIO_PuPd_UP},
     {_PA_2,                 GPIO_PuPd_KEEP,         GPIO_PuPd_UP},
   ...
};

ameba_sleepcfg

github source code

ameba_sleepcfg.c

Wakeup Mask Setup

For sleep mode, only one CPU is required to wake up to execute the program in some situations. The wakeup mask module is designed to implement this function. In general, in addition to configuring the wakeup mask, it is also necessary to register the wakeup source interrupt so that the specific CPU can handle it upon wakeup.

By setting a wakeup mask, you can choose to wake up only one CPU core. If KM4 is chosen, KM0 will be waked up first and then KM0 will resume KM4.

Users can set the wakeup attribute in sleep_wevent_config[] in ameba_sleepcfg.c to choose which CPU you want to wake up. The wakeup attribute of each wakeup source can be set to WAKEUP_KM4 or WAKEUP_KM0 or WAKEUP_NULL, respectively indicating that this wakeup source is only to wake up KM4, or wake up KM0, or not used as a wakeup source.

/* Wakeup entry can be set to WAKEUP_NULL/WAKEUP_KM4/WAKEUP_KM0 */
WakeEvent_TypeDef sleep_wevent_config[] = {
   //   Module              Wakeup
   {WAKE_SRC_SDIO,          WAKEUP_NULL},
   {WAKE_SRC_AON_WAKEPIN,      WAKEUP_NULL},
   {WAKE_SRC_AON_TIM,        WAKEUP_NULL},
   {WAKE_SRC_Keyscan,        WAKEUP_NULL},
   {WAKE_SRC_PWR_DOWN,        WAKEUP_NULL},
   {WAKE_SRC_BOR,          WAKEUP_NULL},
   {WAKE_SRC_ADC,          WAKEUP_NULL},
   {WAKE_SRC_RTC,          WAKEUP_NULL},
   {WAKE_SRC_CTOUCH,        WAKEUP_NULL},
   {WAKE_SRC_I2C1,          WAKEUP_NULL},
   {WAKE_SRC_I2C0,          WAKEUP_NULL},
   {WAKE_SRC_GPIOB,        WAKEUP_NULL},
   {WAKE_SRC_GPIOA,        WAKEUP_NULL},
   {WAKE_SRC_UART_LOG,        WAKEUP_NULL},
   {WAKE_SRC_UART2_BT,        WAKEUP_NULL},
   {WAKE_SRC_UART1,        WAKEUP_NULL},
   {WAKE_SRC_UART0,        WAKEUP_NULL},
   {WAKE_SRC_pmc_timer1,      WAKEUP_KM0},  /* Internal use, do not change it*/
   {WAKE_SRC_pmc_timer0,      WAKEUP_KM4},  /* Internal use, do not change it*/
   {WAKE_SRC_Timer7,        WAKEUP_NULL},
   {WAKE_SRC_Timer6,        WAKEUP_NULL},
   {WAKE_SRC_Timer5,        WAKEUP_NULL},
   {WAKE_SRC_Timer4,        WAKEUP_NULL},
   {WAKE_SRC_IPC_KM4,        WAKEUP_KM4},  /* IPC can only wake up KM4, do not change it*/
   {WAKE_SRC_BT_WAKE_HOST,      WAKEUP_NULL},
   {WAKE_SRC_KM4_WAKE_IRQ,      WAKEUP_KM0},  /* Internal use, do not change it*/
   {WAKE_SRC_WIFI_FTSR_MAILBOX,  WAKEUP_KM0},  /* Wi-Fi wakeup, do not change it*/
   {WAKE_SRC_WIFI_FISR_FESR_IRQ,  WAKEUP_KM0},  /* Wi-Fi wakeup, do not change it*/
   {0xFFFFFFFF,          WAKEUP_NULL},
};

AON Wakepin Configuration

AON wakepin is one of the peripherals that can be set as a wakeup source. SoC has two AON wakepins (PB30 and PB31), which can be configured in sleep_wakepin_config[] in ameba_sleepcfg.c. The config attribute can be set to DISABLE_WAKEPIN or HIGH_LEVEL_WAKEUP or LOW_LEVEL_WAKEUP, meaning not wake up, or GPIO level high will wake up, or GPIO level low will wake up respectively.

/* can be used by sleep mode & deep sleep mode */
/* config can be set to DISABLE_WAKEPIN/HIGH_LEVEL_WAKEUP/LOW_LEVEL_WAKEUP */
WAKEPIN_TypeDef sleep_wakepin_config[] = {
   //   wakepin      config
   {WAKEPIN_0,    DISABLE_WAKEPIN},  /* WAKEPIN_0 corresponding to _PB_30 */
   {WAKEPIN_1,    DISABLE_WAKEPIN},  /* WAKEPIN_1 corresponding to _PB_31 */
   {0xFFFFFFFF,  DISABLE_WAKEPIN},
};

Note

By default, AON_WAKEPIN_IRQ will not be enabled in sleep_wakepin_config[], and users need to enable it by themselves.
The wakeup mask will not be set in sleep_wakepin_config[]. If wakepin is used for sleep mode, WAKE_SRC_AON_WAKEPIN entry needs to be set in sleep_wevent_config[].

Clock and Voltage Configuration

The XTAL, OSC4M state, and sleep mode voltage are configurable in ps_config[] in ameba_sleepcfg.c. Users can use this configuration for peripherals that need XTAL or OSC4M on in sleep mode.

PSCFG_TypeDef ps_config = {
   .keep_OSC4M_on = FALSE,        /* Keep OSC4M on or off for sleep */
   .xtal_mode_in_sleep = XTAL_OFF,    /* Set XTAL mode during sleep mode, see enum xtal_mode_sleep for details */
   .sleep_to_08V = FALSE,        /* Default sleep to 0.7V, setting this option to TRUE will sleep to 0.8V */
};

Sleep mode Configuration

Application software can set sleep mode to CG or PG by calling pmu_set_sleep_type(uint32_t type)().
Users can get CPU’s sleep mode by calling pmu_get_sleep_type().

Note

KM0 and KM4 are in the same power domain, so they will have the same sleep type, thus pmu_set_sleep_type() should be set to KM4, and KM0 will follow KM4’s sleep mode type.
Sleep mode is set to PG by default. If users want to change the sleep type, pmu_set_sleep_type() needs to be called before sleep.

github source code

ameba_sleepcfg.c

Wakeup Mask Setup

For sleep mode, only one CPU is required to wake up to execute the program in some situations. The wakeup mask module is designed to implement this function. In general, in addition to configuring the wakeup mask, it is also necessary to register the wakeup source interrupt so that the specific CPU can handle it upon wakeup.

To enable a specific wakeup source, the corresponding status in array sleep_wevent_config[] in ameba_sleepcfg.c should be set. Each module can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP. For example, if the WAKE_SRC_AON_WAKEPIN module is set to WAKEUP_NP, it means that when the system is in sleep mode, KR4 will be woken up at the time that an aon_wakepin interrupt happens.

/*wakeup attribute can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP/WAKEUP_DSP*/
WakeEvent_TypeDef sleep_wevent_config[] = {
   //  Module                       wakeup
   {WAKE_SRC_VAD,                   WAKEUP_NULL},
   {WAKE_SRC_AON_WAKEPIN,           WAKEUP_NULL},
   {WAKE_SRC_AON_TIM,               WAKEUP_NULL},
   {WAKE_SRC_PWR_DOWN,              WAKEUP_NULL},
   {WAKE_SRC_BOR,                   WAKEUP_NULL},
   {WAKE_SRC_ADC,                   WAKEUP_NULL},
   {WAKE_SRC_AON_RTC,               WAKEUP_NULL},
   {WAKE_SRC_SPI1,                  WAKEUP_NULL},
   {WAKE_SRC_SPI0,                  WAKEUP_NULL},
   {WAKE_SRC_CTOUCH,                WAKEUP_NULL},
   {WAKE_SRC_GPIOB,                 WAKEUP_NULL},
   {WAKE_SRC_GPIOA,                 WAKEUP_NULL},
   {WAKE_SRC_UART_LOG,              WAKEUP_AP},
   {WAKE_SRC_UART3,                 WAKEUP_NULL},
   {WAKE_SRC_UART2,                 WAKEUP_NULL},
   {WAKE_SRC_UART1,                 WAKEUP_NULL},
   {WAKE_SRC_UART0,                 WAKEUP_NULL},
   {WAKE_SRC_Timer7,                WAKEUP_NULL},
   {WAKE_SRC_Timer6,                WAKEUP_NULL},
   {WAKE_SRC_Timer5,                WAKEUP_NULL},
   {WAKE_SRC_Timer4,                WAKEUP_NULL},
   {WAKE_SRC_Timer3,                WAKEUP_NULL},
   {WAKE_SRC_Timer2,                WAKEUP_NULL},
   {WAKE_SRC_Timer1,                WAKEUP_NULL},
   {WAKE_SRC_Timer0,                WAKEUP_NULL},
   {WAKE_SRC_WDG0,                  WAKEUP_NULL},
   {WAKE_SRC_BT_WAKE_HOST,          WAKEUP_NULL},
   {WAKE_SRC_AP_WAKE,               WAKEUP_NULL},
   {WAKE_SRC_WIFI_FTSR_MAILBOX,     WAKEUP_NP},
   {WAKE_SRC_WIFI_FISR_FESR,        WAKEUP_NP},
   {0xFFFFFFFF,                     WAKEUP_NULL},
};

AON Wakepin Configuration

AON wakepin is one of the peripherals that can be set as a wakeup source. SoC has two AON wakepins (PA0 and PA1), which can be configured in sleep_wakepin_config[] in ameba_sleepcfg.c. The config attribute can be set to DISABLE_WAKEPIN or HIGH_LEVEL_WAKEUP or LOW_LEVEL_WAKEUP, meaning not wake up, or GPIO level high will wake up, or GPIO level low will wake up respectively.

/* can be used by sleep mode & deep sleep mode */
/* config can be set to DISABLE_WAKEPIN/HIGH_LEVEL_WAKEUP/LOW_LEVEL_WAKEUP */
WAKEPIN_TypeDef sleep_wakepin_config[] = {
   //   wakepin      config
   {WAKEPIN_0,    DISABLE_WAKEPIN},  /* WAKEPIN_0 corresponding to _PA_0 */
   {WAKEPIN_1,    DISABLE_WAKEPIN},  /* WAKEPIN_1 corresponding to _PA_1 */
   {0xFFFFFFFF,  DISABLE_WAKEPIN},
};

Note

By default, AON_WAKEPIN_IRQ will not be enabled in sleep_wakepin_config[], and users need to enable it by themselves.
The wakeup mask will not be set in sleep_wakepin_config[]. If wakepin is used for sleep mode, WAKE_SRC_AON_WAKEPIN entry needs to be set in sleep_wevent_config[].

Clock and Voltage Configuration

The XTAL, OSC4M state, and sleep mode voltage are configurable in ps_config[] in ameba_sleepcfg.c. Users can use this configuration for peripherals that need XTAL or OSC4M on in sleep mode.

PSCFG_TypeDef ps_config = {
   .keep_OSC4M_on = FALSE,       /* keep OSC4M on or off for sleep */
   .xtal_mode_in_sleep = XTAL_OFF,   /* set xtal mode during sleep mode, see enum xtal_mode_sleep for detail */
};

Sleep Type Configuration

Application software can set sleep mode to CG or PG by calling pmu_set_sleep_type(uint32_t type)(), and users can get CPU’s sleep mode by calling pmu_get_sleep_type().

Note

KR4 and KM4 are in the same power domain, so they will have the same sleep type, thus pmu_set_sleep_type() should be set to AP, and NP will follow AP’s sleep mode type.
Sleep mode is set to PG by default. If users want to change the sleep type, pmu_set_sleep_type() needs to be called before sleep.

github source code

ameba_sleepcfg.c

Wakeup Mask Setup

For sleep mode, only one CPU is required to wake up to execute the program in some situations. The wakeup mask module is designed to implement this function. In general, in addition to configuring the wakeup mask, it is also necessary to register the wakeup source interrupt so that the specific CPU can handle it upon wakeup.

To enable a specific wakeup source, the corresponding status in array sleep_wevent_config[] in ameba_sleepcfg.c should be set. Each module can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP/WAKEUP_DSP. For example, if the WAKE_SRC_AON_WAKEPIN module is set to WAKEUP_NP, it means that when the system is in sleep mode, KR4 will be woken up at the time that an aon_wakepin interrupt happens.

/*wakeup attribute can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP/WAKEUP_DSP*/
WakeEvent_TypeDef sleep_wevent_config[] = {
   //  Module                       wakeup
   {WAKE_SRC_VAD,                   WAKEUP_NULL},
   {WAKE_SRC_AON_WAKEPIN,           WAKEUP_NULL},
   {WAKE_SRC_AON_TIM,               WAKEUP_NULL},
   {WAKE_SRC_PWR_DOWN,              WAKEUP_NULL},
   {WAKE_SRC_BOR,                   WAKEUP_NULL},
   {WAKE_SRC_ADC,                   WAKEUP_NULL},
   {WAKE_SRC_AON_RTC,               WAKEUP_NULL},
   {WAKE_SRC_SPI1,                  WAKEUP_NULL},
   {WAKE_SRC_SPI0,                  WAKEUP_NULL},
   {WAKE_SRC_CTOUCH,                WAKEUP_NULL},
   {WAKE_SRC_GPIOB,                 WAKEUP_NULL},
   {WAKE_SRC_GPIOA,                 WAKEUP_NULL},
   {WAKE_SRC_UART_LOG,              WAKEUP_AP},
   {WAKE_SRC_UART3,                 WAKEUP_NULL},
   {WAKE_SRC_UART2,                 WAKEUP_NULL},
   {WAKE_SRC_UART1,                 WAKEUP_NULL},
   {WAKE_SRC_UART0,                 WAKEUP_NULL},
   {WAKE_SRC_Timer7,                WAKEUP_NULL},
   {WAKE_SRC_Timer6,                WAKEUP_NULL},
   {WAKE_SRC_Timer5,                WAKEUP_NULL},
   {WAKE_SRC_Timer4,                WAKEUP_NULL},
   {WAKE_SRC_Timer3,                WAKEUP_NULL},
   {WAKE_SRC_Timer2,                WAKEUP_NULL},
   {WAKE_SRC_Timer1,                WAKEUP_NULL},
   {WAKE_SRC_Timer0,                WAKEUP_NULL},
   {WAKE_SRC_WDG0,                  WAKEUP_NULL},
   {WAKE_SRC_BT_WAKE_HOST,          WAKEUP_NULL},
   {WAKE_SRC_AP_WAKE,               WAKEUP_NULL},
   {WAKE_SRC_WIFI_FTSR_MAILBOX,     WAKEUP_NP},
   {WAKE_SRC_WIFI_FISR_FESR,        WAKEUP_NP},
   {0xFFFFFFFF,                     WAKEUP_NULL},
};

AON Wakepin Configuration

AON wakepin is one of the peripherals that can be set as a wakeup source. SoC has two AON wakepins (PA0 and PA1), which can be configured in sleep_wakepin_config[] in ameba_sleepcfg.c. The config attribute can be set to DISABLE_WAKEPIN or HIGH_LEVEL_WAKEUP or LOW_LEVEL_WAKEUP, meaning not wake up, or GPIO level high will wake up, or GPIO level low will wake up respectively.

/* can be used by sleep mode & deep sleep mode */
/* config can be set to DISABLE_WAKEPIN/HIGH_LEVEL_WAKEUP/LOW_LEVEL_WAKEUP */
WAKEPIN_TypeDef sleep_wakepin_config[] = {
   //   wakepin      config
   {WAKEPIN_0,    DISABLE_WAKEPIN},  /* WAKEPIN_0 corresponding to _PA_0 */
   {WAKEPIN_1,    DISABLE_WAKEPIN},  /* WAKEPIN_1 corresponding to _PA_1 */
   {0xFFFFFFFF,  DISABLE_WAKEPIN},
};

Note

By default, AON_WAKEPIN_IRQ will not be enabled in sleep_wakepin_config[], and users need to enable it by themselves.
The wakeup mask will not be set in sleep_wakepin_config[]. If wakepin is used for sleep mode, WAKE_SRC_AON_WAKEPIN entry needs to be set in sleep_wevent_config[].

Clock and Voltage Configuration

The XTAL, OSC4M state, and sleep mode voltage are configurable in ps_config[] in ameba_sleepcfg.c. Users can use this configuration for peripherals that need XTAL or OSC4M on in sleep mode.

PSCFG_TypeDef ps_config = {
   .keep_OSC4M_on = FALSE,       /* keep OSC4M on or off for sleep */
   .xtal_mode_in_sleep = XTAL_OFF,   /* set xtal mode during sleep mode, see enum xtal_mode_sleep for detail */
};

Sleep Type Configuration

Application software can set sleep mode to CG or PG by calling pmu_set_sleep_type(uint32_t type)(), and users can get CPU’s sleep mode by calling pmu_get_sleep_type().

Note

KR4 and KM4 are in the same power domain, so they will have the same sleep type, thus pmu_set_sleep_type() should be set to AP, and NP will follow AP’s sleep mode type.
Sleep mode is set to PG by default. If users want to change the sleep type, pmu_set_sleep_type() needs to be called before sleep.

github source code

ameba_sleepcfg.c

Wakeup Mask Setup

For sleep mode, only one CPU is required to wake up to execute the program in some situations. The wakeup mask module is designed to implement this function. In general, in addition to configuring the wakeup mask, it is also necessary to register the wakeup source interrupt so that the specific CPU can handle it upon wakeup.

To enable a specific wakeup source, the corresponding status in array sleep_wevent_config[] in ameba_sleepcfg.c should be set. Each module can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP/WAKEUP_DSP. For example, if the WAKE_SRC_AON_WAKEPIN module is set to WAKEUP_NP, it means that when the system is in sleep mode, KR4 will be woken up at the time that an aon_wakepin interrupt happens.

/*wakeup attribute can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP/WAKEUP_DSP*/
WakeEvent_TypeDef sleep_wevent_config[] = {
   //  Module                       wakeup
   {WAKE_SRC_VAD,                   WAKEUP_NULL},
   {WAKE_SRC_AON_WAKEPIN,           WAKEUP_NULL},
   {WAKE_SRC_AON_TIM,               WAKEUP_NULL},
   {WAKE_SRC_PWR_DOWN,              WAKEUP_NULL},
   {WAKE_SRC_BOR,                   WAKEUP_NULL},
   {WAKE_SRC_ADC,                   WAKEUP_NULL},
   {WAKE_SRC_AON_RTC,               WAKEUP_NULL},
   {WAKE_SRC_SPI1,                  WAKEUP_NULL},
   {WAKE_SRC_SPI0,                  WAKEUP_NULL},
   {WAKE_SRC_CTOUCH,                WAKEUP_NULL},
   {WAKE_SRC_GPIOB,                 WAKEUP_NULL},
   {WAKE_SRC_GPIOA,                 WAKEUP_NULL},
   {WAKE_SRC_UART_LOG,              WAKEUP_AP},
   {WAKE_SRC_UART3,                 WAKEUP_NULL},
   {WAKE_SRC_UART2,                 WAKEUP_NULL},
   {WAKE_SRC_UART1,                 WAKEUP_NULL},
   {WAKE_SRC_UART0,                 WAKEUP_NULL},
   {WAKE_SRC_Timer7,                WAKEUP_NULL},
   {WAKE_SRC_Timer6,                WAKEUP_NULL},
   {WAKE_SRC_Timer5,                WAKEUP_NULL},
   {WAKE_SRC_Timer4,                WAKEUP_NULL},
   {WAKE_SRC_Timer3,                WAKEUP_NULL},
   {WAKE_SRC_Timer2,                WAKEUP_NULL},
   {WAKE_SRC_Timer1,                WAKEUP_NULL},
   {WAKE_SRC_Timer0,                WAKEUP_NULL},
   {WAKE_SRC_WDG0,                  WAKEUP_NULL},
   {WAKE_SRC_BT_WAKE_HOST,          WAKEUP_NULL},
   {WAKE_SRC_AP_WAKE,               WAKEUP_NULL},
   {WAKE_SRC_WIFI_FTSR_MAILBOX,     WAKEUP_NP},
   {WAKE_SRC_WIFI_FISR_FESR,        WAKEUP_NP},
   {0xFFFFFFFF,                     WAKEUP_NULL},
};

AON Wakepin Configuration

AON wakepin is one of the peripherals that can be set as a wakeup source. SoC has two AON wakepins (PA0 and PA1), which can be configured in sleep_wakepin_config[] in ameba_sleepcfg.c. The config attribute can be set to DISABLE_WAKEPIN or HIGH_LEVEL_WAKEUP or LOW_LEVEL_WAKEUP, meaning not wake up, or GPIO level high will wake up, or GPIO level low will wake up respectively.

/* can be used by sleep mode & deep sleep mode */
/* config can be set to DISABLE_WAKEPIN/HIGH_LEVEL_WAKEUP/LOW_LEVEL_WAKEUP */
WAKEPIN_TypeDef sleep_wakepin_config[] = {
   //   wakepin      config
   {WAKEPIN_0,    DISABLE_WAKEPIN},  /* WAKEPIN_0 corresponding to _PA_0 */
   {WAKEPIN_1,    DISABLE_WAKEPIN},  /* WAKEPIN_1 corresponding to _PA_1 */
   {0xFFFFFFFF,  DISABLE_WAKEPIN},
};

Note

By default, AON_WAKEPIN_IRQ will not be enabled in sleep_wakepin_config[], and users need to enable it by themselves.
The wakeup mask will not be set in sleep_wakepin_config[]. If wakepin is used for sleep mode, WAKE_SRC_AON_WAKEPIN entry needs to be set in sleep_wevent_config[].

Clock and Voltage Configuration

The XTAL, OSC4M state, and sleep mode voltage are configurable in ps_config[] in ameba_sleepcfg.c. Users can use this configuration for peripherals that need XTAL or OSC4M on in sleep mode.

PSCFG_TypeDef ps_config = {
   .keep_OSC4M_on = FALSE,       /* keep OSC4M on or off for sleep */
   .xtal_mode_in_sleep = XTAL_OFF,   /* set xtal mode during sleep mode, see enum xtal_mode_sleep for detail */
};

Sleep Type Configuration

Application software can set sleep mode to CG or PG by calling pmu_set_sleep_type(uint32_t type)(), and users can get CPU’s sleep mode by calling pmu_get_sleep_type().

Note

KR4 and KM4 are in the same power domain, so they will have the same sleep type, thus pmu_set_sleep_type() should be set to AP, and NP will follow AP’s sleep mode type.
Sleep mode is set to PG by default. If users want to change the sleep type, pmu_set_sleep_type() needs to be called before sleep.

github source code

ameba_sleepcfg.c

Wakeup Mask Setup

For sleep mode, only one CPU is required to wake up to execute the program in some situations. The wakeup mask module is designed to implement this function. In general, in addition to configuring the wakeup mask, it is also necessary to register the wakeup source interrupt so that the specific CPU can handle it upon wakeup.

By setting a wakeup mask, you can choose to wake up only one CPU core. If KM4 is chosen, KM0 will be waked up first and then KM0 will resume KM4. And if CA32 is chosen, KM0 will be waked up first and then KM0 will resume KM4, and CA32 will be resumed at last.

Users can set the wakeup attribute in sleep_wevent_config[] in ameba_sleepcfg.c to choose which CPU you want to wake up. The wakeup attribute of each wakeup source can be set to WAKEUP_KM4 or WAKEUP_KM0 or WAKEUP_NULL, respectively indicating that this wakeup source is only to wake up KM4, or wake up KM0, or not used as a wakeup source.

/*wakeup attribute can be set to WAKEUP_NULL/WAKEUP_LP/WAKEUP_NP/WAKEUP_AP*/
WakeEvent_TypeDef sleep_wevent_config[] = {
   //  Module                  wakeup
   {WAKE_SRC_nFIQOUT1_OR_nIRQOUT1,      WAKEUP_NULL},
   {WAKE_SRC_nFIQOUT0_OR_nIRQOUT0,      WAKEUP_NULL},
   {WAKE_SRC_BT_WAKE_HOST,          WAKEUP_NULL},
   {WAKE_SRC_AON_WAKEPIN,          WAKEUP_NULL},
   {WAKE_SRC_UART2,            WAKEUP_NULL},
   {WAKE_SRC_UART1,            WAKEUP_NULL},
   {WAKE_SRC_UART0,            WAKEUP_NULL},
   {WAKE_SRC_SPI1,              WAKEUP_NULL},
   {WAKE_SRC_SPI0,              WAKEUP_NULL},
   {WAKE_SRC_IPC_AP,            WAKEUP_AP},    /* do not change it */
   {WAKE_SRC_IPC_NP,            WAKEUP_NP},   /* do not change it*/
   {WAKE_SRC_VADBT_OR_VADPC,        WAKEUP_NULL},
   {WAKE_SRC_PWR_DOWN,            WAKEUP_LP},
   {WAKE_SRC_BOR,              WAKEUP_NULL},
   {WAKE_SRC_ADC,              WAKEUP_NULL},
   {WAKE_SRC_CTOUCH,            WAKEUP_NULL},
   {WAKE_SRC_RTC,              WAKEUP_NULL},
   {WAKE_SRC_GPIOC,            WAKEUP_NULL},
   {WAKE_SRC_GPIOB,            WAKEUP_NULL},
   {WAKE_SRC_GPIOA,            WAKEUP_NULL},
   {WAKE_SRC_UART_LOG,            WAKEUP_NULL},
   {WAKE_SRC_Timer7,            WAKEUP_NULL},
   {WAKE_SRC_Timer6,            WAKEUP_NP},
   {WAKE_SRC_Timer5,            WAKEUP_NULL},
   {WAKE_SRC_Timer4,            WAKEUP_NULL},
   {WAKE_SRC_Timer3,            WAKEUP_NULL},
   {WAKE_SRC_Timer2,            WAKEUP_NULL},
   {WAKE_SRC_Timer1,            WAKEUP_NULL},
   {WAKE_SRC_Timer0,            WAKEUP_NULL},
   {WAKE_SRC_WDG0,              WAKEUP_NULL},
   {WAKE_SRC_AP_WAKE,            WAKEUP_NULL},
   {WAKE_SRC_NP_WAKE,            WAKEUP_NULL},
   {WAKE_SRC_AON_TIM,            WAKEUP_NULL},
   {WAKE_SRC_WIFI_FTSR_MAILBOX,      WAKEUP_LP},    /* Wi-Fi wakeup, do not change it*/
   {WAKE_SRC_WIFI_FISR_FESR,        WAKEUP_LP},    /* Wi-Fi wakeup, do not change it*/
   {0xFFFFFFFF,              WAKEUP_NULL},  /* Table end */
};

AON Wakepin Configuration

AON wakepin is one of the peripherals that can be set as a wakeup source. SoC has four AON wakepins (PB21, PB22, PB23 and PB24), which can be configured in sleep_wakepin_config[] in ameba_sleepcfg.c. The config attribute can be set to DISABLE_WAKEPIN or HIGH_LEVEL_WAKEUP or LOW_LEVEL_WAKEUP, meaning not wake up, or GPIO positive pulse will wake up, or GPIO negative pulse will wake up respectively.

/* can be used by sleep mode & deep sleep mode */
/* config can be set to DISABLE_WAKEPIN/HIGH_LEVEL_WAKEUP/LOW_LEVEL_WAKEUP */
WAKEPIN_TypeDef sleep_wakepin_config[] = {
   //  wakepin      config
   {WAKEPIN_0,    DISABLE_WAKEPIN},  /* WAKEPIN_0 corresponding to _PB_21 */
   {WAKEPIN_1,    DISABLE_WAKEPIN},  /* WAKEPIN_1 corresponding to _PB_22  */
   {WAKEPIN_2,    DISABLE_WAKEPIN},  /* WAKEPIN_2 corresponding to _PB_23  */
   {WAKEPIN_3,    DISABLE_WAKEPIN},  /* WAKEPIN_3 corresponding to _PB_24  */
   {0xFFFFFFFF,  DISABLE_WAKEPIN},  /* Table end */
}

Note

PB23 and PB24 is for loguart trx by default, if PB23 and PB24 is needed to wake up system from dslp, contact realtek for help. Active and sleep mode of pin is controlled by pinmap config, change pmap_func[] in ameba_pinmapcfg.c if needed.
By default, AON_WAKEPIN_IRQ will not be enabled in sleep_wakepin_config[], and users need to enable it by themselves.
The wakeup mask will not be set in sleep_wakepin_config[]. If wakepin is used for sleep mode, WAKE_SRC_AON_WAKEPIN entry needs to be set in sleep_wevent_config[].

Clock and Voltage Configuration

The XTAL, OSC4M state are configurable in ps_config[] in ameba_sleepcfg.c. Users can use this configuration for peripherals that need XTAL or OSC4M on in sleep mode.

PSCFG_TypeDef ps_config = {
   .km0_tickles_debug = TRUE,/* if open WIFI FW, should close it, or beacon will lost in WOWLAN */
   .km0_pll_off = TRUE,
   .km0_audio_vad_on = FALSE,
#if defined(CONFIG_CLINTWOOD ) && CONFIG_CLINTWOOD
   .km0_config_psram = FALSE, /* if device enter sleep mode or not, false for keep active */
   .km0_sleep_withM4 = FALSE,
#else
   .km0_config_psram = TRUE, /* if device enter sleep mode or not, false for keep active */
   .km0_sleep_withM4 = TRUE,
#endif
   .keep_OSC4M_on = FALSE,
   .xtal_mode_in_sleep = XTAL_OFF,
   .swr_mode_in_sleep = SWR_PFM,
};

github source code

ameba_sleepcfg.c

Wakeup Mask Configuration

In sleep mode, some scenarios only require a single CPU to be woken up to execute code. The wakeup mask module is designed for this purpose. Typically, in addition to setting the wakeup mask, it is also necessary to register the interrupt of the wakeup source so that it can be handled by the specified CPU upon waking.

By configuring the wakeup mask, you can choose to wake up only a designated CPU. If you select KM4TZ (default Application Core, AP), KM4NS (default Network Core, NP) must be woken up first and then resume KM4TZ operation.

Users can select the target CPU to wake up by modifying the sleep_wevent_config[] array in ameba_sleepcfg.c.

Each wakeup source can be configured with one of the following attributes:

WAKEUP_AP: Wake up KM4TZ only
WAKEUP_NP: Wake up KM4NS only
WAKEUP_NULL: Disable this wakeup source

/* Wakeup attributes can be set to WAKEUP_NULL/WAKEUP_NP/WAKEUP_AP */
struct WakeEvent_TypeDef sleep_wevent_config[] = {
    //        Module                                                          Wakeup
      {WAKE_SRC_SDIO_WIFI,                                    WAKEUP_NULL},
      {WAKE_SRC_BT_WAKE_HOST,                                 WAKEUP_NULL},
      {WAKE_SRC_BT_SCB,                                               WAKEUP_NULL},
      {WAKE_SRC_CAN1,                                                 WAKEUP_NULL},
      {WAKE_SRC_CAN0,                                                 WAKEUP_NULL},
      {WAKE_SRC_USB,                                                  WAKEUP_NULL},
      {WAKE_SRC_SDIO_HOST,                                    WAKEUP_NULL},
      {WAKE_SRC_SDIO_BT,                                              WAKEUP_NULL},
      {WAKE_SRC_AON_WAKEPIN,                                  WAKEUP_NULL},
      {WAKE_SRC_AON_TIM,                                              WAKEUP_NULL},
      {WAKE_SRC_RMII,                                                 WAKEUP_NULL},
      {WAKE_SRC_PWR_DOWN,                                             WAKEUP_NULL},
      {WAKE_SRC_BOR,                                                  WAKEUP_NULL},
      {WAKE_SRC_CAPTOUCH,                                             WAKEUP_NULL},
      {WAKE_SRC_ADC,                                                  WAKEUP_NULL},
      {WAKE_SRC_RTC,                                                  WAKEUP_NULL},
      {WAKE_SRC_GPIOC,                                                WAKEUP_NULL},
      {WAKE_SRC_GPIOB,                                                WAKEUP_NULL},
      {WAKE_SRC_GPIOA,                                                WAKEUP_AP},
      {WAKE_SRC_UART_LOG,                                             WAKEUP_NULL},
      {WAKE_SRC_UART3,                                                WAKEUP_NULL},
      {WAKE_SRC_UART2,                                                WAKEUP_NULL},
      {WAKE_SRC_UART1,                                                WAKEUP_NULL},
      {WAKE_SRC_UART0,                                                WAKEUP_NULL},
      {WAKE_SRC_pmc_timer1,                                   WAKEUP_NP},             /* internal usage, do not change it */
      {WAKE_SRC_pmc_timer0,                                   WAKEUP_AP},             /* internal usage, do not change it */
      {WAKE_SRC_Timer3,                                               WAKEUP_NULL},
      {WAKE_SRC_Timer2,                                               WAKEUP_NULL},
      {WAKE_SRC_Timer1,                                               WAKEUP_NULL},
      {WAKE_SRC_Timer0,                                               WAKEUP_NULL},
      {WAKE_SRC_IWDG,                                                 WAKEUP_NULL},
      {WAKE_SRC_AP_WAKE_IRQ,                                  WAKEUP_NP},
      {WAKE_SRC_WIFI_FTSR_MAILBOX_IRQ,                WAKEUP_NP},             /* For WiFi wakeup, do not change it */
      {WAKE_SRC_WIFI_FISR_FESR_IRQ,                   WAKEUP_NP},             /* For WiFi wakeup, do not change it */
      {0xFFFFFFFF,                                                    WAKEUP_NULL},   /* Table end */
};

AON Wake Pin Configuration

AON wake pins are among the peripherals that support waking up from sleep mode.

The SoC provides four AON wake pins (PA3/PA2/PA1/PA0), which must be configured in the sleep_wakepin_config[] array in ameba_sleepcfg.c.

Available configuration options:

DISABLE_WAKEPIN: Disable wakeup
HIGH_LEVEL_WAKEUP: GPIO high level triggers wakeup
LOW_LEVEL_WAKEUP: GPIO low level triggers wakeup

/* can be used by sleep mode & deep sleep mode */
/* config can be set to DISABLE_WAKEPIN/HIGH_LEVEL_WAKEUP/LOW_LEVEL_WAKEUP */
WAKEPIN_TypeDef sleep_wakepin_config[] = {
   //   wakepin      config
   {WAKEPIN_0,    DISABLE_WAKEPIN},  /* WAKEPIN_0 maps to _PA_3 */
   {WAKEPIN_1,    DISABLE_WAKEPIN},  /* WAKEPIN_1 maps to _PA_2 */
   {WAKEPIN_2,    DISABLE_WAKEPIN},  /* WAKEPIN_2 maps to _PA_1 */
   {WAKEPIN_3,    DISABLE_WAKEPIN},  /* WAKEPIN_3 maps to _PA_0 */
   {0xFFFFFFFF,  DISABLE_WAKEPIN},
};

Note

By default, AON_WAKEPIN_IRQ is not enabled in sleep_wakepin_config[]; users need to manually activate it.
The wakeup mask is not set in sleep_wakepin_config[]. If you want to use the wake pin for sleep mode, set WAKE_SRC_AON_WAKEPIN in sleep_wevent_config[] accordingly.

Clock and Voltage Configuration

The status of XTAL and OSC4M, as well as sleep mode voltage, can be configured through the ps_config[] array in ameba_sleepcfg.c. This is useful in scenarios that require peripheral clocks to remain on during sleep.

PSCFG_TypeDef ps_config = {
   .keep_osc4m_on_in_sleep = FALSE,        /* Keep OSC4M on or off for sleep */
   .xtal_mode_in_sleep = XTAL_OFF,         /* Set XTAL mode during sleep mode, see enum xtal_mode_sleep for details */
   .regu_state_in_sleep = STATE1_LDOPC_SWRPFM_07,        /* Default sleep voltage to 0.7V */
};

Sleep Mode Configuration

The application can set the sleep mode to CG or PG by calling pmu_set_sleep_type(uint32_t type)()
Users can get the current CPU sleep mode by calling pmu_get_sleep_type()

Note

KM4TZ and KM4NS share the same power domain, so their sleep mode is identical. When calling pmu_set_sleep_type() to set the sleep mode of KM4TZ, KM4NS will automatically synchronize with KM4TZ.
The default system sleep mode is PG. If you need to change the sleep mode, you must call pmu_set_sleep_type() before entering sleep.

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